专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07292065B2 Enhanced passgate structures for reducing leakage current 有权
标题翻译：增强型门窗结构，减少漏电流
公开(公告)号：US07292065B2
公开(公告)日：2007-11-06
申请号：US10910891
申请日：2004-08-03
申请人： Henry Y. Lui , Malik Kabani , Rakesh Patel , Tim Tri Hoang
发明人： Henry Y. Lui , Malik Kabani , Rakesh Patel , Tim Tri Hoang
IPC分类号： H03K19/173
CPC分类号： H03K19/1778 , H03K19/17784 , H03K19/17792
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate activation voltage is higher in voltage than a nominal voltage being supplied to circuitry other than the passgate structures.
摘要翻译：提出了在低压系统中使用的增强型门控结构，其中通道结构的操作速度最大化，同时使结构“OFF”时的漏电流最小化。在一种布置中，栅极结构的栅极相对于根据特定工艺尺寸制造的其它晶体管的V IN T T T T增加。此外，通道激活电压被施加到通道结构，使得通电门激活电压的电压高于提供给非门电路结构以外的电路的标称电压。

2. 发明授权

US07046174B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US07046174B1
公开(公告)日：2006-05-16
申请号：US11147757
申请日：2005-06-07
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0331
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

3. 发明授权

US06724328B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06724328B1
公开(公告)日：2004-04-20
申请号：US10454626
申请日：2003-06-03
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M900
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

4. 发明授权

US07003423B1 Programmable logic resource with data transfer synchronization 有权
标题翻译：可编程逻辑资源与数据传输同步
公开(公告)号：US07003423B1
公开(公告)日：2006-02-21
申请号：US10741593
申请日：2003-12-18
申请人： Malik Kabani , Henry Lui
发明人： Malik Kabani , Henry Lui
IPC分类号： G01R27/28 , G01M19/00 , G06F1/04
CPC分类号： G06F1/24 , G06F1/12
摘要： A more time-efficient and area-efficient approach is provided to synchronize the transfer of data into programmable logic resources. A programmable logic resource core clock and a reset signal are routed to a reset register that controls the reset of a dynamic phase alignment circuit and a data realigner. The dynamic phase alignment circuit includes a phase-locked loop circuit, a J counter, and a deserializer. When the output signal of the reset register transitions from logic 1 to logic 0, the J counter begins to count and sets an enable signal accordingly. The enable signal, which controls the output of synchronized parallel data from the deserializer, is therefore phase associated with the programmable logic resource core clock. The synchronized parallel data is input to a data realigner which outputs the data based on the programmable logic resource core clock for input to the programmable logic resource core circuitry.
摘要翻译：提供了一种更节省时间和面积效率的方法来同步数据传输到可编程逻辑资源。可编程逻辑资源核心时钟和复位信号被路由到控制动态相位对准电路和数据重新定标器的复位的复位寄存器。动态相位对准电路包括锁相环电路，J计数器和解串器。当复位寄存器的输出信号从逻辑1转换到逻辑0时，J计数器开始计数并相应地设置使能信号。因此，控制来自解串器的同步并行数据的输出的使能信号与可编程逻辑资源核心时钟相关。同步并行数据被输入到数据重新定标器，该数据重新定标器基于可编程逻辑资源核心时钟输出数据，用于输入到可编程逻辑资源核心电路。

5. 发明申请

US20060028240A1 ENHANCED PASSGATE STRUCTURES FOR REDUCING LEAKAGE CURRENT 有权
标题翻译：用于降低泄漏电流的增强通孔结构
公开(公告)号：US20060028240A1
公开(公告)日：2006-02-09
申请号：US10910891
申请日：2004-08-03
申请人： Henry Lui , Malik Kabani , Rakesh Patel , Tim Hoang
发明人： Henry Lui , Malik Kabani , Rakesh Patel , Tim Hoang
IPC分类号： H03K19/173
CPC分类号： H03K19/1778 , H03K19/17784 , H03K19/17792
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate activation voltage is higher in voltage than a nominal voltage being supplied to circuitry other than the passgate structures.
摘要翻译：提出了在低压系统中使用的增强型门控结构，其中通道结构的操作速度最大化，同时使结构“OFF”时的漏电流最小化。在一种布置中，栅极结构的栅极相对于根据特定工艺尺寸制造的其它晶体管的V IN T T T T增加。此外，通道激活电压被施加到通道结构，使得通电门激活电压的电压高于提供给非门电路结构以外的电路的标称电压。

6. 发明授权

US06970117B1 Byte alignment for serial data receiver 失效
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06970117B1
公开(公告)日：2005-11-29
申请号：US10789406
申请日：2004-02-26
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00 , H04L7/02
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式