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1. 发明申请

US20140233944A1 OPTICAL NETWORK TERMINAL (ONT) WAVELENGTH TUNING AND CORREPSONDING CALIBRATION PROCEDURE 有权
标题翻译：光网络终端（ONT）波长调谐和剔除校准程序
公开(公告)号：US20140233944A1
公开(公告)日：2014-08-21
申请号：US14179660
申请日：2014-02-13
申请人： Peter Vetter , Alex Duque , Robert L. Farah , Joseph L. Galaro , Man Fai Lau , Wolfgang W. Poehlmann , Dora van Veen , Haibo Wen
发明人： Peter Vetter , Alex Duque , Robert L. Farah , Joseph L. Galaro , Man Fai Lau , Wolfgang W. Poehlmann , Dora van Veen , Haibo Wen
IPC分类号： H04J14/02 , H04B10/079
CPC分类号： H04J14/0282 , H04J14/0256
摘要： Tuning an optical network unit (ONU) to an appropriate communication wavelength may be performed by initiating an activation procedure responsive to receiving a wavelength configuration message, and identifying an instruction in the wavelength configuration message to modify a present wavelength used by the network unit to a different wavelength. The process may also provide assigning an optical network unit identifier (ONU-ID) to the network unit, modifying the present wavelength to the different wavelength, and transmitting subsequent data messages from the network unit at the different wavelength.
摘要翻译：将光网络单元（ONU）调谐到适当的通信波长可以通过响应于接收波长配置消息而启动激活过程来执行，并且识别波长配置消息中的指令以将网络单元使用的当前波长修改为不同波长。该过程还可以向网络单元分配光网络单元标识符（ONU-ID），将当前波长修改为不同波长，以及以不同波长从网络单元发送后续数据消息。

2. 发明申请

US20120079236A1 SCALABLE AND PROGRAMMABLE PROCESSOR COMPRISING MULTIPLE COOPERATING PROCESSOR UNITS 有权
标题翻译：包含多个协同处理器单元的可扩展和可编程处理器
公开(公告)号：US20120079236A1
公开(公告)日：2012-03-29
申请号：US13248869
申请日：2011-09-29
申请人： Dusan Suvakovic , Adriaan J. de Lind van Wijngaarden , Man Fai Lau
发明人： Dusan Suvakovic , Adriaan J. de Lind van Wijngaarden , Man Fai Lau
IPC分类号： G06F9/312 , G06F15/76
CPC分类号： G06F15/7867 , G06F9/3897 , Y02D10/12 , Y02D10/13
摘要： A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.
摘要翻译：处理器包括多个处理器单元，其被布置为并行地并且彼此协作地操作，以及控制逻辑，其被配置为指导处理器单元的操作。至少一个处理器单元中的一个包括存储器，算术引擎和交换结构。交换结构提供了存储器，算术引擎和给定处理器单元的输入和输出端口之间的可控连接，并具有由控制逻辑的相应输出驱动的控制输入。在说明性实施例中，处理器单元可以被配置为执行与里德 - 所罗门（RS）解码器或其他类型的前向纠错（FEC）解码器中的密钥方程解算器相关联的计算。

3. 发明授权

US09369207B2 Apparatus and method for two-stage optical network 有权
标题翻译：两级光网络的装置与方法
公开(公告)号：US09369207B2
公开(公告)日：2016-06-14
申请号：US13296784
申请日：2011-11-15
申请人： Dusan Suvakovic , Hungkei K. Chow , Man-Fai Lau , Peter J. Vetter
发明人： Dusan Suvakovic , Hungkei K. Chow , Man-Fai Lau , Peter J. Vetter
IPC分类号： H04B10/291 , H04B10/272 , H04Q11/00
CPC分类号： H04B10/291 , H04B10/272 , H04Q11/0067 , H04Q2011/0079
摘要： A manner of providing an energy-efficient two-stage PON using a multistage-PON repeater to forward data traffic and other communications between the first stage and the second stage. The multistage-PON repeater receives BI-PON transmission frames from and OLT and decimates them, forwarding data intended for end devices of the second stage. The multistage-PON repeater rate adapts the transmissions so that faster speeds may be associated with PON first stage communications and slower speeds are associated with PON second stage communications. Many though not all of the multistage-PON components are configured to operate at the slower clock speed, conserving energy. Upstream transmissions from the end devices of the second stage are buffered in the multistage-PON repeater and forwarded to the OLT according to an allocation schedule received from the OLT in a BI-PON frame.
摘要翻译：使用多级PON中继器提供能量效率的两级PON以在第一级和第二级之间转发数据业务和其他通信的方式。多级PON中继器从OLT接收BI-PON传输帧并对其进行抽取，转发用于第二级终端设备的数据。多级PON中继器速率适应传输，使得更快的速度可能与PON第一级通信相关联，并且较慢的速度与PON第二级通信相关联。许多虽然并非所有的多级PON组件都配置为以较慢的时钟速度运行，但节约能源。来自第二级的终端设备的上行传输被缓存在多级PON中继器中，并且根据在BI-PON帧中从OLT接收的分配调度被转发到OLT。

4. 发明申请

US20120121265A1 Apparatus And Method For Two-Stage Optical Network 有权
标题翻译：两级光网络的装置与方法
公开(公告)号：US20120121265A1
公开(公告)日：2012-05-17
申请号：US13296784
申请日：2011-11-15
申请人： Dusan Suvakovic , Hungkei K. Chow , Man-Fai Lau , Peter J. Vetter
发明人： Dusan Suvakovic , Hungkei K. Chow , Man-Fai Lau , Peter J. Vetter
IPC分类号： H04J14/00
CPC分类号： H04B10/291 , H04B10/272 , H04Q11/0067 , H04Q2011/0079
摘要： A manner of providing an energy-efficient two-stage PON using a multistage-PON repeater to forward data traffic and other communications between the first stage and the second stage. The multistage-PON repeater receives BI-PON transmission frames from and OLT and decimates them, forwarding data intended for end devices of the second stage. The multistage-PON repeater rate adapts the transmissions so that faster speeds may be associated with PON first stage communications and slower speeds are associated with PON second stage communications. Many though not all of the multistage-PON components are configured to operate at the slower clock speed, conserving energy. Upstream transmissions from the end devices of the second stage are buffered in the multistage-PON repeater and forwarded to the OLT according to an allocation schedule received from the OLT in a BI-PON frame.
摘要翻译：使用多级PON中继器提供能量效率的两级PON以在第一级和第二级之间转发数据业务和其他通信的方式。多级PON中继器从OLT接收BI-PON传输帧并对其进行抽取，转发用于第二级终端设备的数据。多级PON中继器速率适应传输，使得更快的速度可能与PON第一级通信相关联，并且较慢的速度与PON第二级通信相关联。许多虽然并非所有的多级PON组件都配置为以较慢的时钟速度运行，但节约能源。来自第二级的终端设备的上行传输被缓存在多级PON中继器中，并且根据在BI-PON帧中从OLT接收的分配调度被转发到OLT。

5. 发明授权

US09996499B2 Scalable and programmable processor comprising multiple cooperating processor units 有权
公开(公告)号：US09996499B2
公开(公告)日：2018-06-12
申请号：US13248869
申请日：2011-09-29
申请人： Dusan Suvakovic , Adriaan J. de Lind van Wijngaarden , Man Fai Lau
发明人： Dusan Suvakovic , Adriaan J. de Lind van Wijngaarden , Man Fai Lau
IPC分类号： G06F15/78 , G06F9/38
CPC分类号： G06F15/7867 , G06F9/3897 , Y02D10/12 , Y02D10/13
摘要： A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.

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