专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09418011B2 Region based technique for accurately predicting memory accesses 有权
标题翻译：用于准确预测存储器访问的基于区域的技术
公开(公告)号：US09418011B2
公开(公告)日：2016-08-16
申请号：US12821935
申请日：2010-06-23
申请人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
发明人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0862 , G06F12/10 , G06F12/1027 , G06F2212/6024
摘要： In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.
摘要翻译：在一个实施例中，本发明包括一个包括页面跟踪缓冲器（PTB）的处理器，该PTB包括多个条目以将地址存储到高速缓存页面并且存储签名以跟踪对高速缓存的每个高速缓存行的访问页面和PTB处理程序，PTB处理程序将条目加载到PTB中并更新签名。还描述和要求保护其他实施例。

2. 发明申请

US20110320762A1 REGION BASED TECHNIQUE FOR ACCURATELY PREDICTING MEMORY ACCESSES 有权
标题翻译：准确预测存储器访问的基于区域的技术
公开(公告)号：US20110320762A1
公开(公告)日：2011-12-29
申请号：US12821935
申请日：2010-06-23
申请人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
发明人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/10
CPC分类号： G06F12/0862 , G06F12/10 , G06F12/1027 , G06F2212/6024
摘要： In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.
摘要翻译：在一个实施例中，本发明包括一个包括页面跟踪缓冲器（PTB）的处理器，该PTB包括多个条目以将地址存储到高速缓存页面并且存储签名以跟踪对高速缓存的每个高速缓存行的访问页面和PTB处理程序，PTB处理程序将条目加载到PTB中并更新签名。还描述和要求保护其他实施例。

3. 发明授权

US08990506B2 Replacing cache lines in a cache memory based at least in part on cache coherency state information 有权
标题翻译：至少部分地基于高速缓存一致性状态信息来替换缓存存储器中的高速缓存行
公开(公告)号：US08990506B2
公开(公告)日：2015-03-24
申请号：US12639191
申请日：2009-12-16
申请人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
发明人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/00 , G06F12/12 , G06F12/08
CPC分类号： G06F12/121 , G06F12/084 , G06F12/126
摘要： In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括高速缓存存储器，其包括高速缓存行，每个高速缓存行具有包括状态部分的标签字段，该状态部分存储存储在该行中的数据的高速缓存一致性状态，以及权重部分，用于存储对应于数据。在各种实现中，权重可以基于高速缓存一致性状态和数据的使用的新近。描述和要求保护其他实施例。

4. 发明申请

US20110145506A1 Replacing Cache Lines In A Cache Memory 有权
标题翻译：更换高速缓存内存中的高速缓存行
公开(公告)号：US20110145506A1
公开(公告)日：2011-06-16
申请号：US12639191
申请日：2009-12-16
申请人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
发明人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/121 , G06F12/084 , G06F12/126
摘要： In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括高速缓存存储器，其包括高速缓存行，每个高速缓存行具有包括状态部分的标签字段，该状态部分存储存储在该行中的数据的高速缓存一致性状态，以及权重部分，用于存储对应于数据。在各种实现中，权重可以基于高速缓存一致性状态和数据的使用的新近。描述和要求保护其他实施例。

5. 发明授权

US09424191B2 Scalable coherence for multi-core processors 有权
标题翻译：多核处理器的可扩展一致性
公开(公告)号：US09424191B2
公开(公告)日：2016-08-23
申请号：US13539044
申请日：2012-06-29
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/0831 , G06F12/08
CPC分类号： G06F12/0817 , G06F12/0815 , Y02D10/13
摘要： An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based coherence directory is coupled with the plurality of cores and is to track sharing of data among the plurality of cores. The cluster sharing map-based coherence directory includes a tag array to store corresponding pairs of addresses and cluster identifiers. Each of the addresses is to identify data. Each of the cluster identifiers is to identify one of the clusters. The cluster sharing map-based coherence directory also includes a cluster sharing map array to store cluster sharing maps. Each of the cluster sharing maps corresponds to one of the pairs of addresses and cluster identifiers. Each of the cluster sharing maps is to indicate intra-cluster sharing of data identified by the corresponding address within a cluster identified by the corresponding cluster identifier.
摘要翻译：一个方面的装置包括多个芯。多个核心被逻辑地分组成多个群集。集群共享基于映射的一致性目录与多个核心耦合，并且用于跟踪多个核心之间的数据共享。集群共享基于映射的一致性目录包括用于存储对应的地址对和集群标识符的标签阵列。每个地址都是识别数据。每个集群标识符用于标识其中一个集群。集群共享基于映射的一致性目录还包括一个集群共享映射数组来存储集群共享映射。每个集群共享映射对应于一对地址和集群标识符。每个集群共享映射是指示由由对应的集群标识符标识的集群内的相应地址所标识的数据的集群内共享。

6. 发明授权

US08683136B2 Apparatus and method for improving data prefetching efficiency using history based prefetching 有权
标题翻译：用于使用基于历史的预取来提高数据预取效率的装置和方法
公开(公告)号：US08683136B2
公开(公告)日：2014-03-25
申请号：US12976775
申请日：2010-12-22
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.
摘要翻译：描述了用于执行基于历史的预取的装置和方法。例如，根据一个实施例的方法包括：确定存储器中是否存在与当前流相关联的存储器页面的先前访问签名; 如果存在先前的访问签名，则从存储器读取先前的访问签名; 并使用先前的访问签名发出预取操作。

7. 发明申请

US20120166733A1 APPARATUS AND METHOD FOR IMPROVING DATA PREFETCHING EFFICIENCY USING HISTORY BASED PREFETCHING 有权
标题翻译：使用基于历史的预编译改进数据预取效率的装置和方法
公开(公告)号：US20120166733A1
公开(公告)日：2012-06-28
申请号：US12976775
申请日：2010-12-22
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.
摘要翻译：描述了用于执行基于历史的预取的装置和方法。例如，根据一个实施例的方法包括：确定存储器中是否存在与当前流相关联的存储器页面的先前访问签名; 如果存在先前的访问签名，则从存储器读取先前的访问签名; 并使用先前的访问签名发出预取操作。

8. 发明申请

US20140006714A1 SCALABLE COHERENCE FOR MULTI-CORE PROCESSORS 有权
标题翻译：多核处理器的可缩放相关性
公开(公告)号：US20140006714A1
公开(公告)日：2014-01-02
申请号：US13539044
申请日：2012-06-29
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0815 , Y02D10/13
摘要： An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based coherence directory is coupled with the plurality of cores and is to track sharing of data among the plurality of cores. The cluster sharing map-based coherence directory includes a tag array to store corresponding pairs of addresses and cluster identifiers. Each of the addresses is to identify data. Each of the cluster identifiers is to identify one of the clusters. The cluster sharing map-based coherence directory also includes a cluster sharing map array to store cluster sharing maps. Each of the cluster sharing maps corresponds to one of the pairs of addresses and cluster identifiers. Each of the cluster sharing maps is to indicate intra-cluster sharing of data identified by the corresponding address within a cluster identified by the corresponding cluster identifier.
摘要翻译：一个方面的装置包括多个芯。多个核心被逻辑地分组成多个群集。集群共享基于映射的一致性目录与多个核心耦合，并且用于跟踪多个核心之间的数据共享。集群共享基于映射的一致性目录包括用于存储对应的地址对和集群标识符的标签阵列。每个地址都是识别数据。每个集群标识符用于标识其中一个集群。集群共享基于映射的一致性目录还包括一个集群共享映射数组来存储集群共享映射。每个集群共享映射对应于一对地址和集群标识符。每个集群共享映射是指示由由对应的集群标识符标识的集群内的相应地址所标识的数据的集群内共享。

9. 发明申请

US20090254712A1 ADAPTIVE CACHE ORGANIZATION FOR CHIP MULTIPROCESSORS 审中-公开
标题翻译：自适应高速缓存组织用于芯片多重处理器
公开(公告)号：US20090254712A1
公开(公告)日：2009-10-08
申请号：US12061027
申请日：2008-04-02
申请人： Naveen Cherukuri , Ioannis Schoinas , Akhilesh Kumar , Seungjoon Park , Ching-Tsun Chou
发明人： Naveen Cherukuri , Ioannis Schoinas , Akhilesh Kumar , Seungjoon Park , Ching-Tsun Chou
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/084 , G06F2212/271
摘要： A method, chip multiprocessor tile, and a chip multiprocessor with amorphous caching are disclosed. An initial processing core 404 may retrieve a data block from a data storage. An initial amorphous cache bank 410 adjacent to the initial processing core 404 may store an initial data block copy 422. A home bank directory 424 may register the initial data block copy 422.
摘要翻译：公开了一种方法，芯片多处理器瓦片和具有非晶缓存的芯片多处理器。初始处理核心404可以从数据存储器检索数据块。与初始处理核心404相邻的初始非晶缓存组410可以存储初始数据块副本422.归属库目录424可以注册初始数据块拷贝422。

10. 发明申请

US20140112145A1 SCHEME FOR AVOIDING DEADLOCK IN MULTI-RING INTERCONNECT, WITH ADDITIONAL APPLICATION TO CONGESTION CONTROL 审中-公开
标题翻译：在多环互连中避免死锁的方案，附加应用于控制控制
公开(公告)号：US20140112145A1
公开(公告)日：2014-04-24
申请号：US14141877
申请日：2013-12-27
申请人： Ching-Tsun Chou , Naveen Cherukuri
发明人： Ching-Tsun Chou , Naveen Cherukuri
IPC分类号： H04L12/801
CPC分类号： H04L47/13 , H04L12/43 , H04L12/4637
摘要： A method and system to avoid multi-ring deadlock. The method includes removing a message on a multi-ring interconnect either with a ring connector associated with the target of the message or by the message's source station such that the message travels no more than one time around the slotted ring interconnect before its removal. The method may also be applied to single ring networks for congestion control.
摘要翻译：一种避免多环死锁的方法和系统。该方法包括通过与消息的目标相关联的环形连接器或由消息的源站去除多环互连上的消息，使得消息在其移除之前不超过一个时间在时隙环互连周围传播。该方法也可以应用于单环网络进行拥塞控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式