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1. 发明授权

US08234540B2 Error correcting code protected quasi-static bit communication on a high-speed bus 失效
标题翻译：在高速总线上纠错代码保护的准静态位通信
公开(公告)号：US08234540B2
公开(公告)日：2012-07-31
申请号：US12165788
申请日：2008-07-01
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

2. 发明申请

US20120146712A1 DESIGN STRUCTURE FOR A REFERENCE VOLTAGE GENERATOR FOR ANALOG TO DIGITAL CONVERTERS 失效
标题翻译：用于模拟数字转换器的参考电压发生器的设计结构
公开(公告)号：US20120146712A1
公开(公告)日：2012-06-14
申请号：US12966624
申请日：2010-12-13
申请人： Lukas Kull , Martin L. Schmatz
发明人： Lukas Kull , Martin L. Schmatz
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , H03M1/0863 , H03M1/12
摘要： A design structure is provided for a reference voltage generator. The design structure includes a first capacitor and an analog to digital converter having its voltage reference coupled to the first capacitor. The first capacitor supplies the voltage reference to the analog to digital converter. A control loop is configured to resupply charges to the first capacitor that are lost when the first capacitor supplies the voltage reference to the analog to digital converter.
摘要翻译：为参考电压发生器提供了一种设计结构。该设计结构包括第一电容器和模数转换器，其电压基准耦合到第一电容器。第一个电容为模数转换器提供电压参考。控制回路被配置为当第一电容器向模数转换器提供电压基准时向第一电容器补充电荷，所述第一电容器将丢失。

3. 发明授权

US07885365B2 Low-power, low-area high-speed receiver architecture 有权
标题翻译：低功耗，低面积高速接收机架构
公开(公告)号：US07885365B2
公开(公告)日：2011-02-08
申请号：US11848599
申请日：2007-08-31
申请人： Christoph Hagleitner , Christian I. Menolfi , Martin L. Schmatz , Thomas H. Toifl
发明人： Christoph Hagleitner , Christian I. Menolfi , Martin L. Schmatz , Thomas H. Toifl
IPC分类号： H04L7/00
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/091 , H03L7/10 , H04L7/0008
摘要： A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.
摘要翻译：高速接收机包括多个接收机组件。每个接收器组件包括用于接收数据的采样锁存器，用于控制由采样锁存器采样数据的定时的相位旋转器以及用于提供时钟和数据恢复的时钟跟踪逻辑级。时钟跟踪逻辑级分为高速早/晚（E / L）逻辑和聚合计数器部分以及由同步逻辑块分隔的低速逻辑部分。接收机还包括用于接收对应于接收数据的数据速率的输入时钟信号的延迟锁定环路（DLL），提供时钟信号的粗略的延迟调整，并将对应于经调整的时钟信号的多个时钟相位矢量输出到相位每个接收器组件上的旋转器。相位旋转器基于从DLL接收的时钟相位矢量来控制数据的采样。单个稳压电源调节器调节提供给DLL和相位旋转器的电源。

4. 发明申请

US20100005365A1 ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效
标题翻译：高速总线上的错误纠正代码保护的静态位通信
公开(公告)号：US20100005365A1
公开(公告)日：2010-01-07
申请号：US12165788
申请日：2008-07-01
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/09
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

5. 发明申请

US20090202076A1 Communications System via Data Scrambling and Associated Methods 有权
标题翻译：通过数据加扰和相关方法的通信系统
公开(公告)号：US20090202076A1
公开(公告)日：2009-08-13
申请号：US12028953
申请日：2008-02-11
申请人： Daniel M. Dreps , Frank D. Ferralolo , Robert J. Reese , Martin L. Schmatz
发明人： Daniel M. Dreps , Frank D. Ferralolo , Robert J. Reese , Martin L. Schmatz
IPC分类号： H04L9/00 , H04K1/00
CPC分类号： H04L25/03866
摘要： A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.
摘要翻译：可以包括通过通信网络连接的发射机，接收机的通信系统。通信网络上的通信链路可以在发射机和接收机之间传送数据。系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。

6. 发明授权

US07478259B2 System, method and storage medium for deriving clocks in a memory system 失效
标题翻译：用于在存储器系统中导出时钟的系统，方法和存储介质
公开(公告)号：US07478259B2
公开(公告)日：2009-01-13
申请号：US11263344
申请日：2005-10-31
申请人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
发明人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：一种用于在存储器系统中导出时钟的系统，方法和存储介质。该方法包括在集线器装置处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

7. 发明授权

US07403073B2 Phase locked loop and method for adjusting the frequency and phase in the phase locked loop 有权
标题翻译：锁相环和相位锁相环调频方法
公开(公告)号：US07403073B2
公开(公告)日：2008-07-22
申请号：US11469423
申请日：2006-08-31
申请人： Marcel A. Kossel , Thomas E. Morf , Martin L. Schmatz , Silvan Wehrli
发明人： Marcel A. Kossel , Thomas E. Morf , Martin L. Schmatz , Silvan Wehrli
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03L7/089 , H03L7/18
摘要： A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
摘要翻译：一种锁相环（PLL），其包括与时间数字转换器耦合的相位频率检测器，其能够将参考信号与振荡器信号进行比较，并产生表示参考信号和振荡器信号之间的相位差的数字值。 PLL还包括能够根据数字值产生控制值的相位获取状态机，以及能够根据控制值产生振荡器信号的可控振荡器。

8. 发明申请

US20080150599A1 METHOD AND APPARATUS FOR GENERATING RANDOM JITTER 失效
标题翻译：用于生成随机抖动器的方法和装置
公开(公告)号：US20080150599A1
公开(公告)日：2008-06-26
申请号：US11828390
申请日：2007-07-26
申请人： Hayden C. Cranford , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H03K3/84
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译：装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为控制脉冲模式发生器。在一个方面，可调电容是至少一个变容二极管。另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到一对变容二极管。确定性抖动发生器可以耦合到脉冲图案发生器。可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。

9. 发明申请

US20080123771A1 Systems and Arrangements for Controlling an Impedance on a Transmission Path 审中-公开
标题翻译：用于控制传输路径阻抗的系统和布置
公开(公告)号：US20080123771A1
公开(公告)日：2008-05-29
申请号：US11557676
申请日：2006-11-08
申请人： Hayden C. Cranford , Daniel J. Friedman , James S. Mason , Martin L. Schmatz , Michael A. Sorna , Thomas H. Toifl
发明人： Hayden C. Cranford , Daniel J. Friedman , James S. Mason , Martin L. Schmatz , Michael A. Sorna , Thomas H. Toifl
IPC分类号： H04B15/00 , H03H7/40
CPC分类号： H04L25/0278
摘要： Systems for making impedance adjustments that will auto-tune a communication path is disclosed. The method can utilize time domain reflectometry (TDR) to acquire data about impedance mismatches and can adjust the termination impedances based on the acquired data. A system is also disclosed that has an isolator to decouple a first adjustable resistor from a transmission path in a first mode and couple the first adjustable resistor to the path in a second mode. The system can have a test transmitter to create a first current on the path in the first mode and to create a second current having twice the current in a second mode, wherein a detector can detect a first voltage during the first mode and a second voltage in the second mode as the first adjustable resistive load is adjusted in the second mode until it reaches a value matching the first voltage detected in the first mode.
摘要翻译：公开了用于进行自动调谐通信路径的阻抗调整的系统。该方法可以利用时域反射（TDR）获取有关阻抗不匹配的数据，并可以根据获取的数据调整终端阻抗。还公开了一种具有隔离器的系统，用于在第一模式中将第一可调电阻器与传输路径去耦，并将第一可调电阻器以第二模式耦合到路径。该系统可以具有测试发射器，以在第一模式中在路径上产生第一电流，并且在第二模式中产生具有两倍电流的第二电流，其中检测器可以在第一模式期间检测第一电压，而第二电压在第二模式中，第一可调电阻负载在第二模式中被调节，直到达到与在第一模式中检测到的第一电压匹配的值。

10. 发明授权

US07088170B2 Multiplexer and demultiplexer 失效
标题翻译：多路复用器和解复用器
公开(公告)号：US07088170B2
公开(公告)日：2006-08-08
申请号：US10827783
申请日：2004-04-20
申请人： Thomas E. Morf , Martin L. Schmatz
发明人： Thomas E. Morf , Martin L. Schmatz
IPC分类号： H03K17/693 , H03K17/62
CPC分类号： H03K17/005 , G11C7/1012
摘要： The multiplexer according to the invention comprises a first data input line (TL1) for incoming data (Data 1), a second data input line (TL2) for incoming data (Data 2), and a data output line (TL3) for outgoing data (Data out). The multiplexer further comprises a control line (20, 21, 22) for applying a control signal (clk) to a first switching means (T1, T3, T5; SR1, SR3, SR5) and a second switching means (T2, T4, T6; SR2, SR4, SR6) for alternatively connecting the first data input line (TL1) over the first switching means (T1, T3, T5; SR1, SR3, SR5) and the second input line (TL2) over the second switching means (T2, T4, T6; SR2, SR4, SR6) to the data output line (TL3), wherein the first and second switching means (T1–T6; SR1–SR6) are spatially arranged in such a way, that the control signal (clk) applied to the first switching means (T1, T3, T5; SR1, SR3, SR5) compared with the control signal (clk) applied to the second switching means (T2, T4, T6; SR2, SR4, SR6) shows a phase shift.
摘要翻译：根据本发明的多路复用器包括用于输入数据（数据1）的第一数据输入线（TL1），用于输入数据（数据2）的第二数据输入线（TL 2）和数据输出线（TL 3）用于输出数据（Data out）。多路复用器还包括用于向第一切换装置（T 1，T 3，T 5; SR 1，SR 3，SR 5）施加控制信号（clk）的控制线（20,21,22）和第二切换用于将第一数据输入线（TL1）交替地连接在第一开关装置（T 1，T 3，T 5; SR 1，T 5，SR 4，SR 6）上的装置（T 2，T 4，T 6; SR 2， SR 3，SR 5）和第二输入线（TL 2）通过第二切换装置（T 2，T 4，T 6; SR 2，SR 4，SR 6）发送到数据输出线（TL 3）第一和第二切换装置（T 1 -T 6; SR 1 -SR 6）以这样的方式空间地布置，即施加到第一切换装置的控制信号（clk）（T 1，T 3，T 5; SR2，SR4，SR6）与施加到第二开关装置（T 2，T 4，T 6; SR 2，SR 4，SR 6）的控制信号（clk）相比较，

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