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1. 发明申请

US20180248558A1 DYNAMIC POWER SWITCHING IN CURRENT-STEERING DACS 审中-公开
公开(公告)号：US20180248558A1
公开(公告)日：2018-08-30
申请号：US15966066
申请日：2018-04-30
申请人： Maxlinear, Inc.
发明人： Jianyu Zhu
IPC分类号： H03M1/08 , H04B15/02 , H03M1/66 , H03M1/00 , H03M1/74
CPC分类号： H03M1/0863 , H03M1/002 , H03M1/66 , H03M1/664 , H03M1/742 , H04B15/02
摘要： Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.

2. 发明授权

US09853653B2 Error cancellation in a current digital-to-analog converter of a continuous-time sigma-delta modulator 有权
公开(公告)号：US09853653B2
公开(公告)日：2017-12-26
申请号：US15259292
申请日：2016-09-08
申请人： MediaTek Inc.
发明人： Tsung-Kai Kao
IPC分类号： H03M1/06 , H03M1/66 , H03M3/00 , H03M1/08 , H03M1/74
CPC分类号： H03M1/06 , H03M1/0863 , H03M1/66 , H03M1/742 , H03M3/50
摘要： Apparatus and methods for reducing noise and distortion in current digital-to-analog converters (IDACs). Compensating capacitors may be connected to current sources in an IDAC. The compensating capacitors may be driven with signals 5 derived from the output of the IDAC to cancel transient current spikes that would otherwise occur on the output of the IDAC.

3. 发明授权

US09748951B2 Switching circuit 有权
公开(公告)号：US09748951B2
公开(公告)日：2017-08-29
申请号：US15195707
申请日：2016-06-28
申请人： IMEC VZW
发明人： Xiaoqiang Zhang , Mark Ingels
IPC分类号： H04L27/12 , H03K17/687 , H03F1/08 , H03F1/14 , H03F1/32 , H03F3/193 , H03F3/21 , H03F3/217 , H03F3/24 , H03M1/66 , H04L27/20 , H03K17/16 , H03K17/62 , H03M1/08 , H03M1/74
CPC分类号： H03K17/687 , H03F1/086 , H03F1/14 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2178 , H03F3/245 , H03F2200/231 , H03F2200/324 , H03F2200/336 , H03F2200/451 , H03F2200/519 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H03K17/161 , H03K17/164 , H03K17/6292 , H03M1/0863 , H03M1/66 , H03M1/742 , H04L27/20
摘要： A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. The conversion circuit includes a second input terminal for receiving a bias voltage signal. The conversion circuit includes an output terminal for outputting a current. The conversion circuit includes a first and a second switch transistor connected to the first input terminal for receiving the digital signal. The conversion circuit includes a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal. The conversion circuit further includes a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor. The conversion circuit further includes a second branch, wherein the second current source transistor is connected to the output terminal via the second switch transistor.

4. 发明授权

US09716508B1 Dummy signal generation for reducing data dependent noise in digital-to-analog converters 有权
公开(公告)号：US09716508B1
公开(公告)日：2017-07-25
申请号：US15150833
申请日：2016-05-10
申请人： ANALOG DEVICES GLOBAL
发明人： Lin Zhang
IPC分类号： H03M1/06 , H03M1/08 , H03M1/66
CPC分类号： H03M1/0863 , H03M1/0678 , H03M1/687
摘要： Mechanisms for generating dummy signals for use in reducing data dependent noise in DACs are disclosed. Disclosed mechanisms differentiate between odd and even bits of a digital data signal to be converted and generate dummy signals by inverting some of these bits and leaving other bits as they are (i.e. including them in their non-inverted form). One dummy signal is generated as a sequence of bits that is the same as a sequence of bits of a data signal except that every odd bit of the data signal is inverted. An alternative dummy signal is generated as a sequence of bits that is the same as a sequence of bits of a data signal except that every even bit is inverted. Generating dummy signals in this manner eliminates the need to use calibration, feedback, or transition detectors, advantageously resulting in increased timing margins and substantial power savings over existing implementations.

5. 发明授权

US09705520B1 Circuit and method for generating reference signals for hybrid analog-to-digital convertors 有权
公开(公告)号：US09705520B1
公开(公告)日：2017-07-11
申请号：US15380246
申请日：2016-12-15
申请人： STMicroelectronics International N.V.
发明人： Ashish Kumar , Chandrajit Debnath , Pratap Narayan Singh
IPC分类号： H03M1/38 , H03M1/06 , H03M1/12 , H03M1/10
CPC分类号： H03M1/466 , H03M1/0863 , H03M1/1009 , H03M1/124 , H03M1/1245 , H03M1/164 , H03M1/38 , H03M1/44
摘要： An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

6. 发明授权

US09680492B1 Threshold detection with digital correction in analog to digital converters 有权
公开(公告)号：US09680492B1
公开(公告)日：2017-06-13
申请号：US15246369
申请日：2016-08-24
申请人： Xilinx, Inc.
发明人： Brendan Farley , Christophe Erdmann
IPC分类号： H03M1/12 , H03M1/38
CPC分类号： H03M1/0863 , H03M1/462 , H03M1/468
摘要： An analog to digital converter (ADC) includes a comparator and a plurality of capacitor pairs coupled between first and second inputs the comparator, where each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage. The ADC also includes a voltage detection circuit and a state machine that is configured to, upon determining during a first cycle that the sampled voltage across the first and second inputs satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs in a default state such that the sampled analog voltage is unchanged. Otherwise, the state machine is configured to switch the first pair of the plurality of capacitor pairs to change the sampled analog voltage.

7. 发明授权

US09548755B2 Analog-to-digital converter with redundancy for image sensor readout 有权
标题翻译：具有图像传感器读数冗余的模数转换器
公开(公告)号：US09548755B2
公开(公告)日：2017-01-17
申请号：US14323998
申请日：2014-07-03
申请人： Forza Silicon Corporation
发明人： Steven Huang , Ali Mesgarani , Daniel Van Blerkom
IPC分类号： H03M1/14 , H03M1/08 , H03M1/12 , H03M1/46 , H03M1/56
CPC分类号： H03M1/14 , H03M1/0863 , H03M1/123 , H03M1/145 , H03M1/466 , H03M1/56
摘要： Methods and systems for analog-to-digital conversion applicable to an image sensor, such as a CMOS image sensor, in which an ADC comprises built-in redundancy such that the ADC can start its conversion cycle before the ADC input settles to a desired resolution and the ADC can yet accurately convert the ADC input to a digital value with the desired resolution. In a CMOS image sensor, such an ADC configuration enables the pixel readout time to overlap with the ADC conversion time, reducing the total time needed to convert the pixel signal value to a digital value with the desired resolution.
摘要翻译：适用于图像传感器（例如CMOS图像传感器）的模数转换的方法和系统，其中ADC包括内置冗余，使得ADC可以在ADC输入稳定到期望分辨率之前开始其转换周期并且ADC可以将ADC输入精确地转换为具有所需分辨率的数字值。在CMOS图像传感器中，这种ADC配置使得像素读出时间与ADC转换时间重叠，从而减少将像素信号值转换为具有期望分辨率的数字值所需的总时间。

8. 发明申请

US20170005654A1 SWITCHING CIRCUIT 有权
标题翻译：切换电路
公开(公告)号：US20170005654A1
公开(公告)日：2017-01-05
申请号：US15195707
申请日：2016-06-28
申请人： IMEC VZW
发明人： Xiaoqiang Zhang , Mark Ingels
IPC分类号： H03K17/687 , H04L27/20 , H03M1/66
CPC分类号： H03K17/687 , H03F1/086 , H03F1/14 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2178 , H03F3/245 , H03F2200/231 , H03F2200/324 , H03F2200/336 , H03F2200/451 , H03F2200/519 , H03F2200/525 , H03F2200/61 , H03F2200/75 , H03K17/161 , H03K17/164 , H03K17/6292 , H03M1/0863 , H03M1/66 , H03M1/742 , H04L27/20
摘要： A conversion circuit is disclosed. In one aspect, the conversion circuit includes a first input terminal for receiving a digital signal. The conversion circuit includes a second input terminal for receiving a bias voltage signal. The conversion circuit includes an output terminal for outputting a current. The conversion circuit includes a first and a second switch transistor connected to the first input terminal for receiving the digital signal. The conversion circuit includes a first and a second current source transistor connected to the second input terminal for receiving the bias voltage signal. The conversion circuit further includes a first branch, wherein the first switch transistor is connected to the output terminal via the first current source transistor. The conversion circuit further includes a second branch, wherein the second current source transistor is connected to the output terminal via the second switch transistor.
摘要翻译：公开了一种转换电路。一方面，转换电路包括用于接收数字信号的第一输入端。转换电路包括用于接收偏置电压信号的第二输入端。转换电路包括用于输出电流的输出端子。转换电路包括连接到第一输入端的第一和第二开关晶体管，用于接收数字信号。转换电路包括连接到第二输入端的第一和第二电流源晶体管，用于接收偏置电压信号。转换电路还包括第一分支，其中第一开关晶体管经由第一电流源晶体管连接到输出端子。转换电路还包括第二分支，其中第二电流源晶体管经由第二开关晶体管连接到输出端子。

9. 发明授权

US09531399B1 Linearity improvement for high resolution RFDAC 有权
标题翻译：高分辨率RFDAC的线性改善
公开(公告)号：US09531399B1
公开(公告)日：2016-12-27
申请号：US14861216
申请日：2015-09-22
申请人： Intel IP Corporation
发明人： Franz Kuttner
IPC分类号： H03M1/06 , H03M1/00 , H03M1/68 , H03M7/16
CPC分类号： H03M1/0863 , H03M1/0845 , H03M1/687 , H03M1/806 , H03M7/165
摘要： A digital to analog converter (DAC) circuit to convert a digital input signal to an analog output signal, wherein the digital input signal comprises a plurality of Least Significant Bits (LSBs) and a plurality of Most Significant Bits (LSBs). The DAC circuit comprises a line decoder configured to receive the plurality of LSBs of the digital input signal and configured to generate line information based thereon. The DAC circuit further comprises a column decoder configured to receive the plurality of MSBs of the digital input signal and configured to generate column information based thereon. Further, the DAC circuit comprises one or more source cells arranged in a plurality of rows and a plurality of columns, wherein the one or more source cells are configured to be selectively activated and consequently generate an individual output signal based on the line information and the column information respectively.
摘要翻译：一种用于将数字输入信号转换为模拟输出信号的数模转换器（DAC）电路，其中数字输入信号包括多个最低有效位（LSB）和多个最高有效位（LSB）。 DAC电路包括线解码器，其被配置为接收数字输入信号的多个LSB，并且被配置为基于此产生线信息。 DAC电路还包括列解码器，其被配置为接收数字输入信号的多个MSB，并且被配置为基于此产生列信息。此外，DAC电路包括布置成多行和多列的一个或多个源单元，其中一个或多个源单元被配置为选择性地激活，并且因此基于线信息生成单独的输出信号，并且列信息。

10. 发明授权

US09515626B2 Digital/analogue conversion 有权
标题翻译：数字/模拟转换
公开(公告)号：US09515626B2
公开(公告)日：2016-12-06
申请号：US14436648
申请日：2013-10-10
申请人： Cirrus Logic International Semiconductor Limited
发明人： John Paul Lesso
IPC分类号： H03M1/00 , H03G3/00 , H03M1/06 , H03M1/66 , H03M1/08 , H03M1/70
CPC分类号： H03G3/001 , H03M1/0624 , H03M1/0626 , H03M1/0863 , H03M1/66 , H03M1/70
摘要： The application relates to digital to analogue conversion circuits having dynamic gain control. A digital variable gain element (102) may apply gain to an input digital signal (DIN) upstream of a DAC (101) to make better use of the input range of the DAC and an analogue variable gain element (103) applies a compensating analogue gain. Again controller (201) has a gain allocation module (204) for controlling the allocation of gain between said digital and analogue variable gain elements in response to changes in a signal level of the input digital audio signal. In the present invention the gain allocation module is operable in first and second modes of operation where the response to reductions in signal level is slower in the first mode than in the second mode of operation. A low-level detector (202) monitors the input digital audio signal so as to detect a low-level part of the signal and the gain controller changes from the first mode to the second mode following detection of a low-level part of the input digital audio signal. The response of the gain allocation module in the second mode is preferably fast enough such that the digital gain can be changed to a target setting suitable for the low-level part of the signal before it is received at the digital gain element.
摘要翻译：该应用涉及具有动态增益控制的数模转换电路。数字可变增益元件（102）可以对DAC（101）上游的输入数字信号（DIN）施加增益，以更好地利用DAC的输入范围，并且模拟可变增益元件（103）应用补偿模拟获得。再次，控制器（201）具有增益分配模块（204），用于响应于输入数字音频信号的信号电平的变化来控制所述数字和模拟可变增益元件之间的增益分配。在本发明中，增益分配模块可在第一和第二操作模式中操作，其中对第一模式的信号电平降低的响应比在第二操作模式中更慢。低电平检测器（202）监视输入数字音频信号，以便在检测到输入的低电平部分之后检测信号的低电平部分，并且增益控制器从第一模式改变到第二模式数字音频信号。增益分配模块在第二模式中的响应优选地足够快，使得数字增益可以在其在数字增益元件被接收之前被改变为适合于信号的低电平部分的目标设置。

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