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1. 发明授权

US09240495B2 Methods of forming nanoscale floating gate 有权
标题翻译：形成纳米级浮栅的方法
公开(公告)号：US09240495B2
公开(公告)日：2016-01-19
申请号：US13795927
申请日：2013-03-12
申请人： Micron Technology, Inc.
发明人： Gurtej S. Sandhu , D. V. Nirmal Ramaswamy
IPC分类号： H01L21/336 , H01L29/788 , B82Y10/00 , H01L21/28 , H01L27/115 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/8247 , B82Y99/00
CPC分类号： H01L29/788 , B82Y10/00 , B82Y99/00 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/42324 , H01L29/66825 , H01L29/7881 , Y10S977/721 , Y10S977/762
摘要： A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.
摘要翻译：提供了包括覆盖在半导体衬底上的隧道电介质层的存储单元。存储单元还包括具有覆盖隧道介电层的第一部分的浮动栅极和从第一部分延伸的纳米棒形式的第二部分。此外，控制栅极层通过隔间电介质层与浮置栅极分离。

2. 发明授权

US09012887B2 Nanowire growth on dissimilar material 有权
标题翻译：纳米线在不同材料上的生长
公开(公告)号：US09012887B2
公开(公告)日：2015-04-21
申请号：US13279786
申请日：2011-10-24
申请人： Lars Samuelson , Jonas Ohlsson , Thomas Mårtensson , Patrik Svensson
发明人： Lars Samuelson , Jonas Ohlsson , Thomas Mårtensson , Patrik Svensson
IPC分类号： H01L29/06 , H01L31/00 , B81C1/00 , B82Y10/00 , H01L21/02 , H01L33/18
CPC分类号： H01L29/0665 , B81C1/00111 , B82Y10/00 , H01L21/02381 , H01L21/02433 , H01L21/02538 , H01L21/02609 , H01L21/02645 , H01L21/02653 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L33/18 , Y10S438/946 , Y10S438/974 , Y10S977/721 , Y10S977/762 , Y10S977/815 , Y10S977/89 , Y10S977/949
摘要： The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
摘要翻译：本发明涉及在Si衬底（3）上III-V族半导体纳米线（2）的生长。控制的垂直纳米线生长通过在纳米线生长之前采取的步骤来实现，其将III族或V族原子提供给Si衬底的（111）表面以提供III族或V 5族表面终止（4）。还提出了纳米结构的器件，其包括依照预定的器件布局以有序图案生长在Si衬底（3）的（111）表面上并从其突出的多个对准的III-V半导体纳米线（2）。

3. 发明授权

US08536015B2 Memory cell that includes a carbon-based memory element and methods of forming the same 有权
标题翻译：包含碳基记忆元件的记忆单元及其形成方法
公开(公告)号：US08536015B2
公开(公告)日：2013-09-17
申请号：US13351468
申请日：2012-01-17
申请人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
发明人： Roy E. Scheuerlein , Alper Ilkbahar , April D. Schricker
IPC分类号： H01L21/00 , H01L21/06 , H01L29/02 , G11C11/00
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/0002 , G11C13/0009 , G11C13/025 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/285 , H01L51/0048 , Y10S977/712 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/734 , Y10S977/788 , Y10S977/789 , Y10S977/79 , Y10S977/855 , Y10S977/943
摘要： In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
摘要翻译：根据本发明的方面，提供了形成金属 - 绝缘体 - 金属叠层的方法。该方法包括形成第一导电层，在第一导电层上形成电阻率切换碳基材料，并在碳基材料上形成第二导电层，其中碳基材料的厚度不大于十个原子层。还描述了其他方面。

4. 发明申请

US20130187215A1 METHODS OF FORMING NANOSCALE FLOATING GATE 有权
标题翻译：形成纳米浮选门的方法
公开(公告)号：US20130187215A1
公开(公告)日：2013-07-25
申请号：US13795927
申请日：2013-03-12
申请人： MICRON TECHNOLOGY, INC.
发明人： Gurtej S. Sandhu , D.V. Nirmal Ramaswamy
IPC分类号： H01L29/788
CPC分类号： H01L29/788 , B82Y10/00 , B82Y99/00 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/42324 , H01L29/66825 , H01L29/7881 , Y10S977/721 , Y10S977/762
摘要： A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.
摘要翻译：提供了包括覆盖在半导体衬底上的隧道电介质层的存储单元。存储单元还包括具有覆盖隧道介电层的第一部分的浮动栅极和从第一部分延伸的纳米棒形式的第二部分。此外，控制栅极层通过隔间电介质层与浮置栅极分离。

5. 发明授权

US08362577B2 Resonator including a microelectromechanical system structure with first and second structures of silicon layers 有权
标题翻译：谐振器包括具有硅层的第一和第二结构的微机电系统结构
公开(公告)号：US08362577B2
公开(公告)日：2013-01-29
申请号：US13012099
申请日：2011-01-24
申请人： Shogo Inaba , Akira Sato , Toru Watanabe , Takeshi Mori
发明人： Shogo Inaba , Akira Sato , Toru Watanabe , Takeshi Mori
IPC分类号： H01L29/84
CPC分类号： H03H3/0073 , H03H9/1057 , Y10S977/721
摘要： A resonator with a microeletromechanical system structure has a transistor with a gate electrode, a capacitor with an upper and lower electrode, a substrate, a first and second structure of the microelectromechanical system structure, a first silicon layer of the first structure and the upper electrode formed above the substrate, a second silicon layer of the second structure and the gate electrode unit formed above the substrate, and an insulating film formed above the capacitor and the transistor, the insulating film having an opening for placement of the second structure.
摘要翻译：具有微机电系统结构的谐振器具有具有栅电极的晶体管，具有上电极和下电极的电容器，基板，微机电系统结构的第一和第二结构，第一结构的第一硅层和上电极形成在基板上方，第二结构的第二硅层和形成在基板上的栅电极单元，以及形成在电容器和晶体管上方的绝缘膜，绝缘膜具有用于放置第二结构的开口。

6. 发明申请

US20120145990A1 NANOWIRE GROWTH ON DISSIMILAR MATERIAL 审中-公开
标题翻译：纳米材料的纳米生长
公开(公告)号：US20120145990A1
公开(公告)日：2012-06-14
申请号：US13279786
申请日：2011-10-24
申请人： Lars SAMUELSON , Jonas Ohlsson , Thomas Mårtensson , Patrik Svensson
发明人： Lars SAMUELSON , Jonas Ohlsson , Thomas Mårtensson , Patrik Svensson
IPC分类号： H01L33/18 , H01L29/267 , H01L21/205
CPC分类号： H01L29/0665 , B81C1/00111 , B82Y10/00 , H01L21/02381 , H01L21/02433 , H01L21/02538 , H01L21/02609 , H01L21/02645 , H01L21/02653 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L33/18 , Y10S438/946 , Y10S438/974 , Y10S977/721 , Y10S977/762 , Y10S977/815 , Y10S977/89 , Y10S977/949
摘要： The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
摘要翻译：本发明涉及在Si衬底（3）上III-V族半导体纳米线（2）的生长。控制的垂直纳米线生长通过在纳米线生长之前采取的步骤来实现，其将III族或V族原子提供给Si衬底的（111）表面以提供III族或V 5族表面终止（4）。还提出了纳米结构的器件，其包括以符合预定的器件布局的有序图案生长在Si衬底（3）的（111）表面上并从其突出的多个对准的III-V半导体纳米线（2）。

7. 发明申请

US20120001248A1 METHODS OF FORMING NANOSCALE FLOATING GATE 有权
标题翻译：形成纳米浮选门的方法
公开(公告)号：US20120001248A1
公开(公告)日：2012-01-05
申请号：US13231371
申请日：2011-09-13
申请人： Gurtej S. Sandhu , D.V. Nirmal Ramaswamy
发明人： Gurtej S. Sandhu , D.V. Nirmal Ramaswamy
IPC分类号： H01L29/788 , H01L29/06 , B82Y99/00
CPC分类号： H01L29/788 , B82Y10/00 , B82Y99/00 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/42324 , H01L29/66825 , H01L29/7881 , Y10S977/721 , Y10S977/762
摘要： A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer.
摘要翻译：提供了包括覆盖在半导体衬底上的隧道电介质层的存储单元。存储单元还包括具有覆盖隧道介电层的第一部分的浮动栅极和从第一部分延伸的纳米棒形式的第二部分。此外，控制栅极层通过隔间电介质层与浮置栅极分离。

8. 发明授权

US07928432B2 Sensing devices from molecular electronic devices 有权
标题翻译：分子电子设备的感应装置
公开(公告)号：US07928432B2
公开(公告)日：2011-04-19
申请号：US12139218
申请日：2008-06-13
申请人： Colin Nuckolls , Xuefeng Guo , Philip Kim
发明人： Colin Nuckolls , Xuefeng Guo , Philip Kim
IPC分类号： H01L35/24
CPC分类号： G01N33/5438 , B82Y10/00 , C12Q1/002 , G01N27/128 , G01N2610/00 , H01L27/285 , H01L51/0036 , H01L51/0048 , H01L51/0056 , H01L51/0076 , H01L51/0083 , H01L51/0591 , Y10S977/701 , Y10S977/721
摘要： The present invention generally relates to the fabrication of molecular electronics devices from molecular wires and Single Wall Nanotubes (SWNT). In one embodiment, the cutting of a SWNT is achieved by opening a window of small width by lithography patterning of a protective layer on top of the SWNT, followed by applying an oxygen plasma to the exposed SWNT portion. In another embodiment, the gap of a cut SWNT is reconnected by one or more difunctional molecules having appropriate lengths reacting to the functional groups on the cut SWNT ends to form covalent bonds. In another embodiment, the gap of a cut SWNT gap is filled with a self-assembled monolayer from derivatives of novel contorted hexabenzocoranenes. In yet another embodiment, a device based on molecular wire reconnecting a cut SWNT is used as a sensor to detect a biological binding event.
摘要翻译：本发明一般涉及从分子线和单壁纳米管（SWNT）制造分子电子器件。在一个实施例中，通过在SWNT顶部上的保护层的光刻图案化，然后将氧等离子体施加到暴露的SWNT部分，打开小宽度的窗口来实现SWNT的切割。在另一个实施方案中，切割的SWNT的间隙通过一个或多个具有与切割的SWNT末端上的官能团反应形成共价键的适当长度的双功能分子重新连接。在另一个实施方案中，切割的SWNT间隙的间隙填充有自组装单层，由新颖扭转的六苯并三硼酸衍生物填充。在另一个实施例中，使用基于重新连接切割SWNT的分子线的装置作为传感器来检测生物结合事件。

9. 发明申请

US20110033952A1 Sensor for Biomolecules 有权
标题翻译：生物分子传感器
公开(公告)号：US20110033952A1
公开(公告)日：2011-02-10
申请号：US12537063
申请日：2009-08-06
申请人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
发明人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
IPC分类号： G01N33/543 , H01L29/78
CPC分类号： G01N33/54373 , B82Y10/00 , G01N27/3276 , G01N27/4145 , G01N33/543 , H01L29/785 , Y10S977/721 , Y10S977/92 , Y10S977/953
摘要： A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.
摘要翻译：用于生物分子的传感器包括包含未掺杂硅的硅片; 与硅鳍片相邻的源极区域，源极区域包括重掺杂的硅; 与所述硅鳍片相邻的漏极区域，所述漏极区域包括掺杂类型的与所述源极区域相同的掺杂类型的重掺杂硅; 以及覆盖源极区域和漏极区域之间的硅鳍片的外部部分的栅极电介质层，所述栅极电介质包括多个抗体，所述多个抗体被配置为与所述生物分子结合，使得漏极电流流动当生物分子与抗体结合时，在源区和漏区之间变化。

10. 发明授权

US07829445B2 Method of manufacturing a flash memory device 有权
标题翻译：制造闪存装置的方法
公开(公告)号：US07829445B2
公开(公告)日：2010-11-09
申请号：US12289301
申请日：2008-10-24
申请人： Tae-Whan Kim , Jae-Hun Jung , Jae-Won Shin , Jeong-Yong Lee
发明人： Tae-Whan Kim , Jae-Hun Jung , Jae-Won Shin , Jeong-Yong Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/42348 , Y10S977/721 , Y10S977/773
摘要： Provided may be a method of fabricating a flash memory device having metal nano particles. The method of manufacturing a flash memory device may include forming a metal oxide thin layer on a semiconductor substrate, forming a floating gate of an amorphous metal silicon oxide thin layer by performing a thermal treatment process on the semiconductor substrate where the metal oxide thin layer is formed, and forming metal nano particles in the floating gate by projecting an electron beam on the floating gate, the metal nano particles being surrounded by a silicon oxide layer.
摘要翻译：提供制造具有金属纳米颗粒的闪速存储器件的方法。制造闪速存储器件的方法可以包括在半导体衬底上形成金属氧化物薄层，通过在半导体衬底上进行热处理工艺形成非晶金属氧化硅薄层的浮栅，其中金属氧化物薄层为通过在浮动栅极上投射电子束，在浮栅中形成金属纳米粒子，金属纳米粒子被氧化硅层包围。

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