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1. 发明授权

US08174046B1 Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting 失效
标题翻译：使用局部变薄或植入，减少寄生晶体管在基于晶闸管的存储器中的影响
公开(公告)号：US08174046B1
公开(公告)日：2012-05-08
申请号：US11362285
申请日：2006-02-23
申请人： Marc Laurent Tarabbia , Maxim Ershov , Rajesh N. Gupta
发明人： Marc Laurent Tarabbia , Maxim Ershov , Rajesh N. Gupta
IPC分类号： H01L29/74
CPC分类号： H01L29/66393 , H01L27/1027 , H01L27/105 , H01L29/7436
摘要： Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.
摘要翻译：描述了具有包括基于晶闸管的存储器单元的存储器的集成电路的方法和装置。一对基于晶闸管的存储单元通常经由位线区域耦合，其中响应于位线区域是共同的，限定了寄生双极结型晶体管。在另一个实施方案中，一对基于晶闸管的存储单元通常经由阳极区耦合，其中响应于阳极区域是共同的，限定了寄生双极结型晶体管。公共位线或阳极区域分别具有局部变薄的区域，以通过寄生双极结型晶体管抑制该对之间的电荷转移。此外，描述了在绝缘体上硅晶片上形成场效应晶体管的方法，其中响应于至少接近绝缘体层的掺杂剂的增加，由寄生双极晶体管促进电荷转移。

2. 发明授权

US07910394B1 Photodiode with improved charge capacity 有权
标题翻译：具有改善充电容量的光电二极管
公开(公告)号：US07910394B1
公开(公告)日：2011-03-22
申请号：US12060702
申请日：2008-04-01
申请人： Maxim Ershov
发明人： Maxim Ershov
IPC分类号： H01L21/00
CPC分类号： H01L31/103 , H01L27/1461 , H01L27/1463 , H01L27/14689
摘要： A method for forming a photodiode cathode in an integrated circuit imager includes defining and implanting a photodiode cathode region with a photodiode cathode implant dose of a dopant species and defining and implanting an edge region of the photodiode cathode region with a photodiode cathode edge implant dose of a dopant species to form a region of higher impurity concentration than the photodiode cathode impurity concentration.
摘要翻译：在集成电路成像器中形成光电二极管阴极的方法包括限定并注入具有光电二极管阴极注入剂量的掺杂剂物质的光电二极管阴极区域，并用光电二极管阴极边缘植入剂量限定和注入光电二极管阴极区域的边缘区域掺杂物种形成比光电二极管杂质浓度高的杂质浓度区域。

3. 发明授权

US07573077B1 Thyristor-based semiconductor memory device with back-gate bias 失效
标题翻译：具有背栅极偏置的基于晶闸管的半导体存储器件
公开(公告)号：US07573077B1
公开(公告)日：2009-08-11
申请号：US11122932
申请日：2005-05-04
申请人： Maxim Ershov
发明人： Maxim Ershov
IPC分类号： H01L29/74
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/1027 , H01L27/105 , H01L27/1203
摘要： In accordance with an embodiment of the present invention, a thyristor-based semiconductor memory device may comprise an array of thyristor-based memory formed in an SOI wafer. A supporting substrate may be formed with a density of dopants sufficient to assist delivery of a bias level to the backside of an insulating layer beneath a thyristor. Such conductivity within the substrate may allow reliable back-gate control for the gain of a component bipolar device of the thyristor.
摘要翻译：根据本发明的实施例，基于晶闸管的半导体存储器件可以包括形成在SOI晶片中的基于晶闸管的存储器阵列。支撑衬底可以形成为具有足以帮助将偏置电平传递到晶闸管下面的绝缘层的背面的掺杂剂的密度。衬底内的这种导电性可以允许用于晶闸管的部件双极器件的增益的可靠的后栅控制。

4. 发明授权

US07859012B1 Thyristor-based semiconductor memory device with back-gate bias 失效
标题翻译：具有背栅极偏置的基于晶闸管的半导体存储器件
公开(公告)号：US07859012B1
公开(公告)日：2010-12-28
申请号：US12538805
申请日：2009-08-10
申请人： Maxim Ershov
发明人： Maxim Ershov
IPC分类号： H01L29/66
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/1027 , H01L27/105 , H01L27/1203
摘要： In accordance with an embodiment of the present invention, a semiconductor memory device includes an array of thyristor-based memory formed in a silicon-on-insulator (SOI) supporting substrate. A portion of the supporting structure of the SOI substrate has a density of dopants sufficient to assist delivery of a bias to the backside of an insulating layer beneath a thyristor of the thyristor-based semiconductor memory. By enabling biasing of the substrate at the backside of the insulating layer beneath the thyristor, a back-gate control is available for controlling or compensating the gain of a component bipolar device of the thyristor with respect to temperature.
摘要翻译：根据本发明的实施例，半导体存储器件包括形成在绝缘体上硅（SOI））衬底中的基于晶闸管的存储器阵列。 SOI衬底的支撑结构的一部分具有足以有助于将偏压传递到基于晶闸管的半导体存储器的晶闸管之下的绝缘层的背面的掺杂剂的密度。通过在晶闸管下面的绝缘层的背面实现衬底的偏置，可以使用背栅极控制来控制或补偿晶闸管的部件双极器件相对于温度的增益。

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