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1. 发明申请

US20160276332A1 ESD PROTECTION STRUCTURE AND METHOD OF FABRICATION THEREOF 审中-公开
标题翻译： ESD保护结构及其制造方法
公开(公告)号：US20160276332A1
公开(公告)日：2016-09-22
申请号：US14830038
申请日：2015-08-19
申请人： Freescale Semiconductor, Inc.
发明人： Jean Philippe LAINE , Patrice BESSE
IPC分类号： H01L27/02 , H01L29/66 , H01L21/762 , H01L21/761 , H01L29/735 , H01L29/74
CPC分类号： H01L27/0251 , H01L21/761 , H01L21/76283 , H01L29/66393 , H01L29/735 , H01L29/7436
摘要： An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.
摘要翻译：一种ESD保护结构，其形成在隔离沟槽内，并且包括第一掺杂型的第一外围半导体区域，第一掺杂型的第二半导体区域和与形成的第一掺杂类型相反的第二掺杂类型的半导体结构，在第一掺杂类型的半导体区域之间的横向隔离和第一掺杂类型的另外的半导体区域与隔离沟槽之间的隔离。形成第二掺杂型的半导体结构，使得在第一掺杂型的第一半导体区域的周边侧和隔离沟槽的壁之间不形成第二掺杂类型的半导体区域，并且不形成半导体区域第一掺杂类型与除第一掺杂类型的第一半导体区之外的隔离沟槽接触。

2. 发明授权

US09240471B2 SCR with fin body regions for ESD protection 有权
标题翻译： SCR带翅片体区，用于ESD保护
公开(公告)号：US09240471B2
公开(公告)日：2016-01-19
申请号：US14011789
申请日：2013-08-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L27/02 , H01L29/74 , G06F17/50 , H01L29/06 , H01L29/66
CPC分类号： H01L27/0262 , G06F17/5063 , G06F17/5072 , H01L29/0649 , H01L29/0657 , H01L29/66121 , H01L29/66393 , H01L29/7408 , H01L29/7412 , H01L29/742 , H01L29/7436 , H01L29/861
摘要： An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.
摘要翻译：公开了一种静电放电保护电路。一种制造半导体结构的方法包括在n阱中形成包括n阱体接触和阳极之间的第一多个指状物的半导体可控整流器，以及p阱体接触件和阴极在p阱中。

3. 发明授权

US09093463B1 Silicon controlled rectifier for providing electrostatic discharge protection for high voltage integrated circuits 有权
标题翻译：可控硅整流器，用于为高压集成电路提供静电放电保护
公开(公告)号：US09093463B1
公开(公告)日：2015-07-28
申请号：US14537424
申请日：2014-11-10
申请人： Richtek Technology Corporation
发明人： Chung-Yu Hung , Jian-Hsing Lee , Tzu-Cheng Kao , Tsung-Yi Huang
IPC分类号： H01L21/336 , H01L29/66 , H01L29/737
CPC分类号： H01L29/66393 , H01L27/0262 , H01L29/0649 , H01L29/737 , H01L29/87
摘要： A silicon controlled rectifier includes: a substrate; a N well and a P well positioned on a side of the substrate and contact with each other; a first N region and a first P region positioned on an upper surface of the N well and contact with each other; a second N region and a second P region positioned on an upper surface of the P well and contact with each other; a first oxide isolation region isolating the first P region and the second N region; a second oxide isolation region isolating the second N region and the second P region; an anode terminal coupled with the first N region and the first P region; and a cathode terminal coupled with the second N region and the second P region. The first P region has a doping concentration less than 80% of that of the second P region.
摘要翻译：可控硅整流器包括：基板; N阱和P阱定位在基板的一侧并彼此接触; 第一N区和第一P区，位于N阱的上表面并彼此接触; 第二N区和第二P区，位于P阱的上表面并彼此接触; 隔离所述第一P区和所述第二N区的第一氧化物隔离区; 隔离所述第二N区域和所述第二P区域的第二氧化物隔离区域; 与所述第一N区和所述第一P区耦合的阳极端; 以及与第二N区域和第二P区域耦合的阴极端子。第一P区的掺杂浓度小于第二P区的掺杂浓度的80％。

4. 发明申请

US20140175509A1 Lattice Mismatched Hetero-Epitaxial Film 有权
标题翻译：晶格失配异质外延膜
公开(公告)号：US20140175509A1
公开(公告)日：2014-06-26
申请号：US13723563
申请日：2012-12-21
申请人： BENJAMIN CHU-KUNG , VAN LE , ROBERT CHAU , SANSAPTAK DASGUPTA , GILBERT DEWEY , NITI GOEL , JACK KAVALIEROS , MATTHEW METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY ZELICK
发明人： BENJAMIN CHU-KUNG , VAN LE , ROBERT CHAU , SANSAPTAK DASGUPTA , GILBERT DEWEY , NITI GOEL , JACK KAVALIEROS , MATTHEW METZ , NILOY MUKHERJEE , RAVI PILLARISETTY , WILLY RACHMADY , MARKO RADOSAVLJEVIC , HAN WUI THEN , NANCY ZELICK
IPC分类号： H01L29/06
CPC分类号： H01L29/7391 , H01L29/0676 , H01L29/66242 , H01L29/6625 , H01L29/66356 , H01L29/66393 , H01L29/732 , H01L29/735 , H01L29/737 , H01L29/7371 , H01L29/7436 , H01L29/785
摘要： An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.
摘要翻译：一个实施例涉及在衬底上形成EPI膜，其中EPI膜具有与衬底不同的晶格常数。 EPI膜和衬底可以包括不同的材料以共同形成具有例如Si和/或SiGe衬底和III-V或IV膜的异质外延装置。 EPI膜可以是多个EPI层或膜中的一个，并且膜可以包括彼此不同的材料并且可以直接彼此接触。此外，在掺杂浓度和/或掺杂极性方面，多个EPI层可以与另一个不同地被掺杂。一个实施例包括产生水平取向的异质外延结构。另一实施例包括垂直取向的异质外延结构。异质外延结构可以包括例如双极结型晶体管，异质结双极晶体管，晶闸管和隧道场效应晶体管等。本文描述了其它实施例。

5. 发明申请

US20140167202A1 ELECTROSTATIC DISCHARGE RESISTANT DIODES 有权
公开(公告)号：US20140167202A1
公开(公告)日：2014-06-19
申请号：US13714404
申请日：2012-12-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Huiming Bu , Robert J. Gauthier, JR. , Terence B. Hook , Effendi Leobandung , Tenko Yamashita
IPC分类号： H01L29/66 , H01L29/861
CPC分类号： H01L29/66121 , H01L21/84 , H01L27/0255 , H01L27/0262 , H01L29/0649 , H01L29/66136 , H01L29/66393 , H01L29/7436 , H01L29/861 , H01L29/8611
摘要： A diode and a method for an electrostatic discharge resistant diode. The method includes, for example, receiving a wafer. The wafer includes a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. An N-type well is implanted in the silicon substrate. Furthermore, a vertical column of P+ doped epitaxial silicon and a vertical column of N+ doped epitaxial silicon are formed over the N-type well and extend through the BOX layer and the silicon layer. Both vertical columns may form electrical junctions with the N-type well.

6. 发明授权

US08530931B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08530931B2
公开(公告)日：2013-09-10
申请号：US13301698
申请日：2011-11-21
申请人： Masayoshi Asano , Junichi Mitani
发明人： Masayoshi Asano , Junichi Mitani
IPC分类号： H01L29/66
CPC分类号： H01L27/0262 , H01L27/0277 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/402 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66121 , H01L29/66393 , H01L29/66689 , H01L29/7436 , H01L29/7816 , H01L29/87
摘要： A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1≧A2 and B1
摘要翻译：形成在ESD保护元件形成区域中的LDMOS晶体管形成区域中的栅电极，元件隔离膜和漏极区域，以及ESD保护元件形成区域中的元件隔离膜和阳极区域，以满足A1> = A2和B1的关系其中LDMOS晶体管形成区域具有栅电极和元件隔离膜的重叠长度A1以及栅电极和漏区之间的距离B1，并且ESD保护元件形成区域具有栅极的重叠长度A2 电极和元件隔离膜以及栅电极和阳极区之间的距离B2。

7. 发明授权

US08450156B2 Method for producing a thyristor 有权
标题翻译：晶闸管的制造方法
公开(公告)号：US08450156B2
公开(公告)日：2013-05-28
申请号：US13481969
申请日：2012-05-29
申请人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
发明人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
IPC分类号： H01L21/332
CPC分类号： H01L29/78624 , H01L21/26586 , H01L21/84 , H01L27/0262 , H01L27/1203 , H01L29/66393 , H01L29/7436 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.
摘要翻译：在晶闸管的制造方法中，在基板上或上方形成有第一和第二连接区域，第一连接区域掺杂有第一导电类型的掺杂剂原子，并且第二连接区域掺杂有第二导电类型的掺杂剂原子; 第一和第二体区域形成在连接区域之间，其中第一体区形成在第一连接区域和第二体区域之间，第二体区域形成在第一体区域和第二连接区域之间; 所述第一体区掺杂有所述第二导电类型的掺杂剂原子，并且所述第二体区掺杂有所述第一导电类型的掺杂剂原子，其中所述掺杂剂原子在每种情况下使用Vt注入方法引入相应的体区; 在身体区域上或上方形成栅极区域。

8. 发明申请

US20130126911A1 STRESS ENHANCED JUNCTION ENGINEERING FOR LATCHUP SCR 失效
标题翻译：应力增强结构工程用于拉力可控制
公开(公告)号：US20130126911A1
公开(公告)日：2013-05-23
申请号：US13743392
申请日：2013-01-17
申请人： International Business Machines Corporation
发明人： John B. Campi , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra
IPC分类号： H01L29/66
CPC分类号： H01L29/66068 , H01L29/66393 , H01L29/7436
摘要： A latchup silicon controlled rectifier (SCR) includes a p+ region and an n+ region located in a p-well of the latchup SCR; and a p+ region and an n+ region located in a n-well of the latchup SCR, wherein the latchup SCR further comprises one of embedded silicon germanium (eSiGe) in the p+ region in the n-well of the latchup SCR and silicon carbide (SiC) in the n+ region in the p-well of the latchup SCR.
摘要翻译：闭锁可控硅整流器（SCR）包括位于闭锁SCR的p阱中的p +区和n +区; 以及位于所述闭锁SCR的n阱中的p +区域和n +区域，其中所述闭锁SCR还包括所述闭锁SCR的n阱中的p +区域中的嵌入硅锗（eSiGe）中的一种和碳化硅（ SiC）在闭锁SCR的p阱中的n +区域中。

9. 发明申请

US20120252172A1 Method for producing a thyristor 有权
标题翻译：晶闸管的制造方法
公开(公告)号：US20120252172A1
公开(公告)日：2012-10-04
申请号：US13481969
申请日：2012-05-29
申请人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
发明人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
IPC分类号： H01L21/332
CPC分类号： H01L29/78624 , H01L21/26586 , H01L21/84 , H01L27/0262 , H01L27/1203 , H01L29/66393 , H01L29/7436 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions.
摘要翻译：在晶闸管的制造方法中，在基板上或上方形成有第一和第二连接区域，第一连接区域掺杂有第一导电类型的掺杂剂原子，并且第二连接区域掺杂有第二导电类型的掺杂剂原子; 第一和第二体区域形成在连接区域之间，其中第一体区形成在第一连接区域和第二体区域之间，第二体区域形成在第一体区域和第二连接区域之间; 所述第一体区掺杂有所述第二导电类型的掺杂剂原子，并且所述第二体区掺杂有所述第一导电类型的掺杂剂原子，其中所述掺杂剂原子在每种情况下都使用Vt注入法引入所述体区; 在身体区域上或上方形成栅极区域。

10. 发明授权

US08236624B2 Method for producing a thyristor 有权
标题翻译：晶闸管的制造方法
公开(公告)号：US08236624B2
公开(公告)日：2012-08-07
申请号：US12620930
申请日：2009-11-18
申请人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
发明人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
IPC分类号： H01L21/332
CPC分类号： H01L29/78624 , H01L21/26586 , H01L21/84 , H01L27/0262 , H01L27/1203 , H01L29/66393 , H01L29/7436 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.
摘要翻译：在电子部件的制造方法中，在基板上或上方形成第一掺杂连接区域和第二掺杂连接区域，在所述第一掺杂连接区域和所述第二掺杂连接区域之间形成体区; 在身体区域上或上方形成彼此分离的至少两个栅极区域; 通过引入掺杂剂原子来掺杂体区的至少一个部分区域，其中通过形成在至少两个分开的栅极区域之间的至少一个中间区域将掺杂剂原子引入到体区的至少一个部分区域中。

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