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1. 发明授权

US08174046B1 Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting 失效
标题翻译：使用局部变薄或植入，减少寄生晶体管在基于晶闸管的存储器中的影响
公开(公告)号：US08174046B1
公开(公告)日：2012-05-08
申请号：US11362285
申请日：2006-02-23
申请人： Marc Laurent Tarabbia , Maxim Ershov , Rajesh N. Gupta
发明人： Marc Laurent Tarabbia , Maxim Ershov , Rajesh N. Gupta
IPC分类号： H01L29/74
CPC分类号： H01L29/66393 , H01L27/1027 , H01L27/105 , H01L29/7436
摘要： Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.
摘要翻译：描述了具有包括基于晶闸管的存储器单元的存储器的集成电路的方法和装置。一对基于晶闸管的存储单元通常经由位线区域耦合，其中响应于位线区域是共同的，限定了寄生双极结型晶体管。在另一个实施方案中，一对基于晶闸管的存储单元通常经由阳极区耦合，其中响应于阳极区域是共同的，限定了寄生双极结型晶体管。公共位线或阳极区域分别具有局部变薄的区域，以通过寄生双极结型晶体管抑制该对之间的电荷转移。此外，描述了在绝缘体上硅晶片上形成场效应晶体管的方法，其中响应于至少接近绝缘体层的掺杂剂的增加，由寄生双极晶体管促进电荷转移。

2. 发明授权

US08324656B1 Reduction of electrostatic coupling for a thyristor-based memory cell 失效
标题翻译：减少基于晶闸管的存储单元的静电耦合
公开(公告)号：US08324656B1
公开(公告)日：2012-12-04
申请号：US13175676
申请日：2011-07-01
申请人： Rajesh N. Gupta , Marc Laurent Tarabbia , Kevin J. Yang
发明人： Rajesh N. Gupta , Marc Laurent Tarabbia , Kevin J. Yang
IPC分类号： H01L29/74
CPC分类号： H01L27/1203 , G11C11/39 , H01L27/1027 , H01L29/7436
摘要： Embodiments of integrated circuits for mitigating against electrostatic coupling are described. In an embodiment, first gate dielectrics are respectively located over first active regions. First isolation regions are respectively located between the first active regions. Second gate dielectrics are respectively located over second active regions. Second isolation regions are respectively located between the second active regions. In an embodiment, the first active regions are approximately 20 to 80 percent shorter in height/thickness than the second active regions. In another embodiment, the first isolation regions extend above an uppermost surface of the first gate dielectrics while providing gaps between the first isolation regions and sidewalls of the first active regions for receipt of material used in formation of conductive lines. In yet another embodiment, active area stripes are narrower in width at p-base regions and n-base regions than at cathode regions and anode regions respectively thereof.
摘要翻译：描述了用于减轻静电耦合的集成电路的实施例。在一个实施例中，第一栅极电介质分别位于第一有源区上。第一隔离区分别位于第一活性区之间。第二栅极电介质分别位于第二有源区上。第二隔离区域分别位于第二活性区域之间。在一个实施例中，第一活性区域的高度/厚度比第二活性区域短约20至80％。在另一个实施例中，第一隔离区域在第一栅极电介质的最上表面上方延伸，同时在第一隔离区域和第一有源区域的侧壁之间提供间隙，以便接收用于形成导电线路的材料。在另一个实施例中，有源区条纹在p基区和n基区域的宽度分别窄于阴极区和阳极区。

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