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1. 发明授权

US07315268B1 Integrator current matching 有权
标题翻译：集成电流电流匹配
公开(公告)号：US07315268B1
公开(公告)日：2008-01-01
申请号：US11453200
申请日：2006-06-15
申请人： Merit Y. Hong
发明人： Merit Y. Hong
IPC分类号： H03M1/00
CPC分类号： H03M3/362 , H03M3/43 , H03M3/452
摘要： An integrator circuit (110) is provided including an amplifier element (170) configured to receive an input signal at an input node, amplify the input signal, and provide an amplified input signal at an output node; a feedback capacitor element (175) connected between the output node and the input node; and a current matching circuit (120) connected to the output node, and configured to sense an output voltage of the amplifier element and to provide a supplemental current (IM) to the input node that is less than or equal to a feedback current (IF) charging the feedback capacitor element. This supplemental current is substantially equal and opposite in polarity to a feedback current when the output voltage satisfies a set criterion.
摘要翻译：提供积分器电路（110），其包括被配置为在输入节点处接收输入信号的放大器元件（170），放大输入信号，并在输出节点处提供放大的输入信号; 连接在所述输出节点和所述输入节点之间的反馈电容器元件（175）以及电流匹配电路（120），其连接到所述输出节点，并且被配置为感测所述放大器元件的输出电压并且向所述输入节点提供小于所述输入节点的补充电流（I SUB M）或等于对反馈电容器元件充电的反馈电流（I T F F）。当输出电压满足设定的标准时，该补充电流在极性上与反馈电流基本相等。

2. 发明授权

US5886921A Static random access memory cell having graded channel metal oxide semiconductor transistors and method of operation 失效
标题翻译：具有分级沟道金属氧化物半导体晶体管的静态随机存取存储单元及其操作方法
公开(公告)号：US5886921A
公开(公告)日：1999-03-23
申请号：US762171
申请日：1996-12-09
申请人： Robert B. Davies , James S. Caravella , Andreas A. Wild , Merit Y. Hong
发明人： Robert B. Davies , James S. Caravella , Andreas A. Wild , Merit Y. Hong
IPC分类号： G11C11/41 , G11C11/412 , H01L27/11 , G11C11/00
CPC分类号： H01L27/11 , G11C11/41 , G11C11/412
摘要： An SRAM memory cell (40) uses GCMOS transistors (42, 44, 56, and 58) for improving discharge of complementary bit lines (60 and 62). The GCMOS transistors (42, 44, 56, and 58) have a graded-channel region on only the source side of the transistors. Configuring the pass-transistors (56 and 58) having the drain terminals connected to the complementary bit lines (60 and 62) and the cross-coupled transistors (42 and 44) having drain terminals connected to the memory cell outputs improves timing for a read operation of the memory cell (40).
摘要翻译： SRAM存储单元（40）使用GCMOS晶体管（42,44,56和58）来改善互补位线（60和62）的放电。 GCMOS晶体管（42,44,56和58）仅在晶体管的源极侧具有渐变沟道区域。配置具有连接到互补位线（60和62）的漏极端子和具有连接到存储器单元输出的漏极端子的交叉耦合晶体管（42和44）的传输晶体管（56和58）改善了读取的定时存储单元（40）的操作。

3. 发明授权

US07834787B2 Techniques for delay compensation of continuous-time sigma-delta modulators 有权
标题翻译：连续时间Σ-Δ调制器的延迟补偿技术
公开(公告)号：US07834787B2
公开(公告)日：2010-11-16
申请号：US12350492
申请日：2009-01-08
申请人： Merit Y. Hong
发明人： Merit Y. Hong
IPC分类号： H03M1/00
CPC分类号： H03M3/37 , H03M3/424 , H03M3/43 , H03M3/484
摘要： A technique for implementing compensatory feedback in a continuous-time sigma-delta modulator includes providing, based on an analog input signal, a digital output signal at an output of a quantizer circuit of the continuous-time sigma-delta modulator. A functionality of the quantizer circuit is then controlled based on the digital output signal.
摘要翻译：用于在连续时间Σ-Δ调制器中实现补偿反馈的技术包括基于模拟输入信号在连续时间Σ-Δ调制器的量化器电路的输出处提供数字输出信号。然后基于数字输出信号来控制量化器电路的功能。

4. 发明申请

US20100207797A1 DIGITALLY ADJUSTABLE QUANTIZATION CIRCUIT 有权
标题翻译：数字可调量化电路
公开(公告)号：US20100207797A1
公开(公告)日：2010-08-19
申请号：US12388231
申请日：2009-02-18
申请人： David E. Bien , Brandt Braswell , Merit Y. Hong
发明人： David E. Bien , Brandt Braswell , Merit Y. Hong
IPC分类号： H03M1/12 , H03M13/00
CPC分类号： H03M1/0604 , H03M1/365 , H03M7/165
摘要： Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.
摘要翻译：提供了用于将模拟输入信号转换为数字输出值的装置和方法。量化电路包括输入节点和比较器阵列，其中比较器阵列的每个比较器耦合到输入节点。分压器布置耦合到比较器阵列并且被配置为为比较器阵列的每个比较器建立相应的阈值电压。比较器阵列基于每个比较器的输入信号和相应的阈值电压产生数字码。控制节点耦合到分压器装置，其中协调地配置控制节点和分压器装置以响应于控制节点处的控制信号来调整比较器阵列的至少一个比较器的阈值电压。

5. 发明申请

US20100171643A1 Techniques for Delay Compensation of Continuous-Time Sigma-Delta Modulators 有权
标题翻译：连续时间Σ-Δ调制器的延迟补偿技术
公开(公告)号：US20100171643A1
公开(公告)日：2010-07-08
申请号：US12350492
申请日：2009-01-08
申请人： Merit Y. Hong
发明人： Merit Y. Hong
IPC分类号： H03M3/02 , H03M1/06
CPC分类号： H03M3/37 , H03M3/424 , H03M3/43 , H03M3/484
摘要： A technique for implementing compensatory feedback in a continuous-time sigma-delta modulator includes providing, based on an analog input signal, a digital output signal at an output of a quantizer circuit of the continuous-time sigma-delta modulator. A functionality of the quantizer circuit is then controlled based on the digital output signal.
摘要翻译：用于在连续时间Σ-Δ调制器中实现补偿反馈的技术包括基于模拟输入信号在连续时间Σ-Δ调制器的量化器电路的输出处提供数字输出信号。然后基于数字输出信号来控制量化器电路的功能。

6. 发明授权

US07443325B2 Sigma-delta modulator 有权
标题翻译： Sigma-delta调制器
公开(公告)号：US07443325B2
公开(公告)日：2008-10-28
申请号：US11979089
申请日：2007-10-31
申请人： Merit Y. Hong
发明人： Merit Y. Hong
IPC分类号： H03M3/00
CPC分类号： H03M3/362 , H03M3/43 , H03M3/452
摘要： An integrator circuit (110) is provided including an amplifier element (170) configured to receive an input signal at an input node, amplify the input signal, and provide an amplified input signal at an output node; a feedback capacitor element (175) connected between the output node and the input node; and a current matching circuit (120) connected to the output node, and configured to sense an output voltage of the amplifier element and to provide a supplemental current (IM) to the input node that is less than or equal to a feedback current (IF) charging the feedback capacitor element. This supplemental current is substantially equal and opposite in polarity to a feedback current when the output voltage satisfies a set criterion.
摘要翻译：提供积分器电路（110），其包括被配置为在输入节点处接收输入信号的放大器元件（170），放大输入信号，并在输出节点处提供放大的输入信号; 连接在所述输出节点和所述输入节点之间的反馈电容器元件（175）以及电流匹配电路（120），其连接到所述输出节点，并且被配置为感测所述放大器元件的输出电压并且向所述输入节点提供小于所述输入节点的补充电流（I SUB M）或等于对反馈电容器元件充电的反馈电流（I T F F）。当输出电压满足设定的标准时，该补充电流在极性上与反馈电流基本相等。

7. 发明申请

US20100194612A1 SWITCHED-CAPACITOR CIRCUITS, INTEGRATION SYSTEMS, AND METHODS OF OPERATION THEREOF 有权
标题翻译：开关电容电路，集成系统及其运行方法
公开(公告)号：US20100194612A1
公开(公告)日：2010-08-05
申请号：US12363201
申请日：2009-01-30
申请人： Merit Y. Hong , Mohammad Nizam U. Kabir
发明人： Merit Y. Hong , Mohammad Nizam U. Kabir
IPC分类号： H03M3/02 , H03M1/12
CPC分类号： H03M3/464 , H03M3/35 , H03M3/43 , H03M3/47
摘要： Embodiments include integrator systems, switched-capacitor circuits, and methods of their operation. An integrator system comprises a differential amplifier and first and second sampling modules. The first sampling module includes a first capacitor and a first set of switches. The first set of switches changes a connection status between the first capacitor and first and second amplifier input terminals when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and refrains from changing the connection status when the change in the polarity does occur. The second sampling module includes a second capacitor and a second set of switches. The second set of switches changes a connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity does occur, and refrains from changing the connection status when the change in the polarity does not occur.
摘要翻译：实施例包括积分器系统，开关电容器电路及其操作方法。积分器系统包括差分放大器和第一和第二采样模块。第一采样模块包括第一电容器和第一组开关。当在连续的开关周期之间不发生差分输入信号的极性的变化时，第一组开关改变第一电容器与第一和第二放大器输入端子之间的连接状态，并且当改变连接状态时不改变连接状态极性确实发生。第二采样模块包括第二电容器和第二组开关。当发生极性变化时，第二组开关改变第二电容器与第一和第二放大器输入端子之间的连接状态，并且当不发生极性变化时，不改变连接状态。

8. 发明授权

US07323931B2 System and method for operating a feedback network 有权
标题翻译：用于操作反馈网络的系统和方法
公开(公告)号：US07323931B2
公开(公告)日：2008-01-29
申请号：US11389223
申请日：2006-03-27
申请人： Merit Y. Hong , Julian G. Aschieri , Zhou Zhixu
发明人： Merit Y. Hong , Julian G. Aschieri , Zhou Zhixu
IPC分类号： H03F1/36
CPC分类号： H03F1/34 , H03F3/005 , H03F3/45273 , H03F3/45475 , H03F2200/264 , H03F2200/91 , H03F2203/45114 , H03F2203/45224 , H03F2203/45288 , H03F2203/45352 , H03F2203/45356 , H03F2203/45511 , H03F2203/45514
摘要： A method and apparatus are provided for operating a feedback network (300, 400). The method and apparatus operate to combine (240) a feedback signal (IF) and an incoming signal (VIN) to generate an adjusted signal (IADJ) at an input node of an amplifier element (110); amplifying the amplifier input signal in the amplifier element to produce an amplifier output signal (VOUT) at an output node of the amplifier element; processing the amplifier output signal according to a feedback operation (230) to generate the feedback signal (IF); and providing an assist current (350, 450, IASSIST) to the output node of the amplifier element, separate from an output current provided by the amplifier element.
摘要翻译：提供了一种用于操作反馈网络（300,400）的方法和装置。该方法和装置用于组合（240）反馈信号（I SUB）和输入信号（V IN IN IN）以产生经调整的信号（I SUB> ADJ 在放大器元件（110）的输入节点处<！ - SIPO ）; 以及向放大器元件的输出节点提供辅助电流（350,450，I ASSIST），与放大器元件提供的输出电流分开。

9. 发明授权

US5748475A Apparatus and method of orienting asymmetrical semiconductor devices in a circuit 失效
标题翻译：在电路中定向不对称半导体器件的装置和方法
公开(公告)号：US5748475A
公开(公告)日：1998-05-05
申请号：US452899
申请日：1995-05-30
申请人： Merit Y. Hong
发明人： Merit Y. Hong
IPC分类号： G06F17/50 , G06F15/00 , H01L27/10
CPC分类号： G06F17/5045
摘要： A computer implemented method provides for orientation and lay-out asymmetrical semiconductor devices. The sources of operating potential (20, 30) are identified. The PMOS transistors (22-28) are combined between the first (more positive) source of operating potential and a common node (12) into a combination block (48). The NMOS transistors (14-18) are combined between the common node and the second (less positive) source of operating potential into another combination block (52). The PMOS source terminals are coupled to more positive potentials, and the PMOS drain terminals are coupled to less positive potentials within the first combination block. The NMOS source terminals are coupled to less positive potentials, and the NMOS drain terminals are coupled to more positive potentials within the second combination block. For transmission gates (60, 62), a driving source is identified and the PMOS and NMOS source terminals are coupled to the driving source.
摘要翻译：计算机实现的方法提供了取向和布置不对称半导体器件。确定了经营潜力的来源（20,30）。 PMOS晶体管（22-28）在第一（更正）的操作电位源和公共节点（12）之间组合成组合块（48）。 NMOS晶体管（14-18）在公共节点和第二（较少正）的工作电位源之间组合到另一组合块（52）中。 PMOS源极端子耦合到更多的正电位，并且PMOS漏极端子耦合到第一组合块内的较小的正电位。 NMOS源极端子耦合到较小的正电位，并且NMOS漏极端子耦合到第二组合块内的更多正电位。对于传输门（60,62），识别驱动源并且PMOS和NMOS源极端子耦合到驱动源。

10. 发明授权

US07898353B2 Clock conditioning circuit 有权
标题翻译：时钟调理电路
公开(公告)号：US07898353B2
公开(公告)日：2011-03-01
申请号：US12466987
申请日：2009-05-15
申请人： Merit Y. Hong , Bruce M. Newman
发明人： Merit Y. Hong , Bruce M. Newman
IPC分类号： H03K3/00 , H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/15 , G06F1/10
摘要： A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.
摘要翻译：电路包括时钟调节电路，其接收经编码的时钟信号，并响应地提供第一和第二调节时钟信号。时钟调节电路响应于编码时钟信号的周期的调整来调整第一和第二调节时钟信号的周期。该电路包括接收第一和第二调节时钟信号的调制器。

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