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1. 发明申请

US20190222223A1 INPUT PATH MATCHING IN PIPELINED CONTINUOUS-TIME ANALOG-TO-DIGITAL CONVERTERS 审中-公开
公开(公告)号：US20190222223A1
公开(公告)日：2019-07-18
申请号：US16141671
申请日：2018-09-25
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
IPC分类号： H03M3/00 , H03K5/159 , H03M1/00
CPC分类号： H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
摘要： System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

2. 发明授权

US09813077B2 Asynchronous electrical circuitry techniques for producing stationary carrier signal to encode input signal amplitude into output signal time-sequence information 有权
公开(公告)号：US09813077B2
公开(公告)日：2017-11-07
申请号：US15323038
申请日：2015-06-30
申请人： Indice Semiconductor Inc.
发明人： James Hamond , Robert D. Batten
IPC分类号： H03M3/00
CPC分类号： H03M3/50 , H03M3/32 , H03M3/37 , H03M3/39 , H03M3/402 , H03M3/43 , H03M3/458
摘要： Asynchronous electrical circuitry produces a stationary carrier signal and encodes a system input signal amplitude into output signal time-sequence information by establishing at a digitizer an operating point value as an average amplitude of the system input signal. It applies to the digitizer a multicomponent digitizer-input signal corresponding to a sum of a passband signal component and a feedback signal component to produce a pulse-width modulated digitizer output signal representing the system input signal. An asynchronous time delay is introduced to produce the pulse-width modulated system output signal. The circuitry performs digital-to-analog conversion (DAC) to the pulse-width modulated system output signal to produce a DAC output signal. The DAC output signal or its summation with the passband signal component is integrated to produce the feedback signal component. Additional, multiple-order embodiments include sequential feedback paths or carrier-shaping functions.

3. 发明申请

US20170194984A1 VCO-BASED CONTINUOUS-TIME SIGMA DELTA MODULATOR EQUIPPED WITH TRUNCATION CIRCUIT AND PHASE-DOMAIN EXCESS LOOP DELAY COMPENSATION 审中-公开
公开(公告)号：US20170194984A1
公开(公告)日：2017-07-06
申请号：US15461502
申请日：2017-03-17
申请人： MEDIATEK INC.
发明人： Sheng-Jui Huang , Michael A. Ashburn, JR. , Divya Kesharwani , Nathan Egan
IPC分类号： H03M3/00
CPC分类号： H03M3/37 , H03M1/86 , H03M3/422 , H03M3/424 , H03M3/428 , H03M3/464
摘要： A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.

4. 发明申请

US20160269045A1 Input Path Matching in Pipelined Continuous-Time Analog-to-Digital Converters 有权
标题翻译：流水线连续模拟数字转换器中的输入路径匹配
公开(公告)号：US20160269045A1
公开(公告)日：2016-09-15
申请号：US15068231
申请日：2016-03-11
申请人： Texas Instruments Incorporated
发明人： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
IPC分类号： H03M3/00 , H03K5/159
CPC分类号： H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
摘要： System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
摘要翻译：在流水线连续时间模数转换器（ADC）中的输入路径匹配的系统和方法，包括基于流水线连续时间三角调制器（CTDSM）的ADC，包括设置在连续时间输入路径中的输入延迟电路，将模拟输入信号输入到连续时间ADC的第一求和电路。至少一个数字延迟线设置在耦合到第一求和电路的较低级子ADC（多个流水线式子ADC）的输出与子数字 - 模拟转换器（DAC）之间，并且在较低级的副ADC与数字噪声消除滤波器之间。数字延迟线被配置为使得能够根据输入延迟匹配电路的过程变化来校准提供给子DAC和数字噪声消除滤波器的前级子ADC的输出延迟，以最小化残留输出在第一个求和电路。

5. 发明申请

US20160134300A1 SAR ADC AND METHOD THEREOF 有权
标题翻译： SAR ADC及其方法
公开(公告)号：US20160134300A1
公开(公告)日：2016-05-12
申请号：US14919830
申请日：2015-10-22
申请人： MEDIATEK Inc.
发明人： Chi Yun Wang , Jen-Che Tsai , SHU-WEI CHU
IPC分类号： H03M1/46 , H03M1/12 , H03M1/08 , H03M1/42
CPC分类号： H03M1/462 , H03M1/0854 , H03M1/12 , H03M1/1245 , H03M1/38 , H03M1/403 , H03M1/42 , H03M1/466 , H03M1/468 , H03M3/37 , H03M3/458
摘要： A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.
摘要翻译：提供了包括比较器，输入开关单元，正转换电容器阵列，负转换电容器阵列和SAR控制器的SAR ADC。输入开关单元将差分模拟输入信号交替耦合到比较器。正和负转换电容器阵列在采样阶段对差分模拟输入信号进行采样。 SAR控制器在采样阶段结束时复位电容器阵列中的开关，将采样电压改变为残余信号，产生一个中间数字代码，根据比较器的输出在转换阶段控制开关，以转换到中间数字码的残留信号，根据中间数字码产生数字码，并在转换阶段结束时使用反相中间数字码来控制开关。

6. 发明申请

US20160056838A1 Digital Technique For Excess Loop Delay Compensation In A Continuous-Time Delta Sigma Modulator 有权
标题翻译：数字技术在连续时间三角形Σ调制器中的过度循环延迟补偿
公开(公告)号：US20160056838A1
公开(公告)日：2016-02-25
申请号：US14822061
申请日：2015-08-10
申请人： Maxim Integrated Products, Inc.
发明人： Yi ZHANG , Phillip Elliott , Ed Liu , Yang Qian , Geir Ostrem , John Frank Scampini
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M3/37 , H03M3/424 , H03M3/434 , H03M3/454 , H03M3/464 , H03M3/496
摘要： A continuous time delta sigma modulator includes a quantizer, a buffer module, and a reference module. The quantizer includes a comparator that updates a digital output each cycle of a clock signal based on a comparison of a reference potential with an input generated based on a sample of an analog signal. The buffer module receives the digital output, stores the digital output for a predetermined delay period, and outputs the digital output after the predetermined delay period as a delayed digital output. The predetermined delay period is less than one cycle of the clock signal. The reference module selectively varies the reference potential based on the delayed digital output.
摘要翻译：连续时间ΔΣ调制器包括量化器，缓冲器模块和参考模块。量化器包括比较器，其基于参考电位与基于模拟信号的采样产生的输入的比较，更新数字输出每个周期的时钟信号。缓冲器模块接收数字输出，在预定的延迟周期内存储数字输出，并在预定的延迟周期之后输出数字输出作为延迟的数字输出。预定的延迟周期小于时钟信号的一个周期。参考模块基于延迟的数字输出选择性地改变参考电位。

7. 发明申请

US20150358724A1 Feedback Delay Reduction In Force Feedback Devices 有权
标题翻译：反馈延迟降低强制反馈设备
公开(公告)号：US20150358724A1
公开(公告)日：2015-12-10
申请号：US14299346
申请日：2014-06-09
申请人： Robert Bosch GmbH
发明人： Vladimir P. Petkov , Ganesh K. Balachandran
IPC分类号： H04R3/00
CPC分类号： H04R3/00 , H03M3/37 , H03M3/406 , H03M3/422 , H03M3/452 , H03M3/454 , H04R2201/003
摘要： A feedback circuit provides a feedback signal to a transducer. The feedback circuit includes an ADC that generates digital representations of a feedback signal, digital controller that identifies adjustments for the feedback, and DAC that generates an analog output of the adjusted feedback signal. The digital controller performs speculative computation to identify adjustments for the feedback signal output for each output value from the ADC prior to receiving the output from the ADC. The ADC and DAC include sigma-delta modulators that operate with a zero clock cycle delay in a forward path. The ADC, digital controller, and DAC generate adjustments to the feedback output signal with reduced delay that reduce phase lag and improve phase margin to maintain stability in the transducer.
摘要翻译：反馈电路向换能器提供反馈信号。反馈电路包括产生反馈信号的数字表示的ADC，识别反馈的调节的数字控制器以及产生经调整的反馈信号的模拟输出的DAC。在接收ADC的输出之前，数字控制器执行推测计算以识别来自ADC的每个输出值的反馈信号输出的调整。 ADC和DAC包括在正向通路中以零时钟周期延迟运行的Σ-Δ调制器。 ADC，数字控制器和DAC通过减小延迟来产生对反馈输出信号的调整，从而减少相位滞后并提高相位裕度，以保持传感器的稳定性。

8. 发明申请

US20150288380A1 ESTIMATION OF DIGITAL-TO-ANALOG CONVERTER STATIC MISMATCH ERRORS 有权
标题翻译：数字到模拟转换器静态误差错误的估计
公开(公告)号：US20150288380A1
公开(公告)日：2015-10-08
申请号：US14302173
申请日：2014-06-11
申请人： ANALOG DEVICES TECHNOLOGY
发明人： JIALIN ZHAO , RICHARD E. SCHREIER , JOSE BARREIRO SILVA , HAJIME SHIBATA , WENHUA W. YANG , YUNZHI DONG
IPC分类号： H03M3/00
CPC分类号： H03M3/378 , H03M1/1019 , H03M1/1038 , H03M1/74 , H03M3/37 , H03M3/384 , H03M3/388 , H03M3/464
摘要： Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).
摘要翻译：数模转换器（DAC）广泛应用于电子产品。 DAC通常不理想，并且通常表现出错误，例如静态失配错误。本公开描述了用于连续时间Δ-Σ调制器（CTDSM）中的DAC静态失配的数字校准技术。该方法利用DAC单元元件（UE）本身来测量彼此的不匹配。没有额外的电路，除了DAC驱动器或比较器中的逻辑设计。该方法是高性能CTDSM的有吸引力的校准技术，特别是对于具有低过采样率（OSR）的多千兆赫兹范围内的高速系统。

9. 发明授权

US08847804B2 Delay compensated continuous time sigma delta analog-to-digital converter 有权
标题翻译：延迟补偿连续时间Σ-Δ模数转换器
公开(公告)号：US08847804B2
公开(公告)日：2014-09-30
申请号：US13668496
申请日：2012-11-05
申请人： Freescale Semiconductor, Inc.
发明人： Brandt Braswell , Luis J. Briones
IPC分类号： H03M3/00
CPC分类号： H03M3/39 , H03M3/344 , H03M3/37 , H03M3/458
摘要： A continuous time sigma delta analog to digital converter is provided. The continuous time sigma delta analog to digital converter may include, but is not limited to, an analog to digital converter having a feedback loop, and a feedback loop controller coupled to the analog to digital converter, the feedback loop controller configured to adjust delay in the feedback loop by controlling a variable delay component in the feedback loop.
摘要翻译：提供了连续的时间Σ-Δ模数转换器。连续时间Σ-Δ模数转换器可以包括但不限于具有反馈回路的模数转换器和耦合到模数转换器的反馈回路控制器，该反馈回路控制器被配置成调整延迟通过控制反馈回路中的可变延迟分量来反馈回路。

10. 发明授权

US08593318B2 Continuous time ΔΣ analog-to-digital converter with a mitigation bit shifting multiplex array 有权
标题翻译：连续时间DeltaSigma模数转换器，具有缓解位移复用阵列
公开(公告)号：US08593318B2
公开(公告)日：2013-11-26
申请号：US13544208
申请日：2012-07-09
申请人： Rune Kaald
发明人： Rune Kaald
IPC分类号： H03M3/00
CPC分类号： H03M3/37 , H03M3/43 , H03M3/452 , H03M3/454
摘要： A continuous time ΔΣ analog-to-digital converter with mitigation bit shifting multiplex array including a loop filter, a VCO responsive to analog signal configured to adjust the output frequency based on the magnitude of the analog signal and produce a digital output, a multi-stage phase quantizer responsive to the digital output configured to determine the phase of the VCO by comparing the phase of the VCO for a particular sample to a reference phase at said particular sample and generate a quantized phase difference value, and a multiplexer array coupled to the multi-stage phase quantizer configured to shift selected misaligned bits of the quantized phase difference value by a predetermined amount of bits to mitigate bit shifting of the multi-stage phase quantizer.
摘要翻译：一种具有缓解位移复用阵列的连续时间DeltaSigma模数转换器，包括环路滤波器，响应于被配置为基于模拟信号幅度调节输出频率并产生数字输出的模拟信号的VCO，所述多级相位量化器响应于所述数字输出被配置为通过将所述特定样本的VCO的相位与所述特定样本处的参考相位进行比较来确定所述VCO的相位，并且生成量化的相位差值，以及耦合到所述多路复用器阵列多级相位量化器被配置为将量化相位差值的选定的未对齐位移位预定量的位以减轻多级相位量化器的位移。

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