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    • 1. 发明授权
      US4493033A Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing 失效
    • Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing
    • 在交替的半周期和同步写入期间具有交错读访问的双端口缓存
    • US4493033A
    • 1985-01-08
    • US447105
    • 1982-12-06
    • Michael L. Ziegler , Michael B. Druke
    • Michael L. Ziegler , Michael B. Druke
    • G06F9/26 , G06F9/318 , G06F11/10 , G06F11/14 , G06F12/08 , G06F12/10 , G06F12/14 , G06F9/00 , G06F13/00
    • G06F9/3017 , G06F11/10 , G06F11/14 , G06F12/0802 , G06F12/0804 , G06F12/0857 , G06F12/1009 , G06F12/14 , G06F9/26 , G06F11/106
    • A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
    • 数据处理系统处理可以从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。 该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。 解码的宏指令提供一个或多个微指令的起始地址，该地址被提供给唯一的微指令排序单元，其适当地解码每个微指令的选定字段以获得每个连续的微指令。 该系统使用八个存储段（环）的分层存储器存储，根据不同级别的权限访问以特权方式控制的环。 存储器系统使用一组主存储器模块，其通过双端口高速缓冲存储器与中央处理器系统连接，在主存储器和高速缓冲存储器之间块数据传输由存储体控制器单元控制。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US4079454A Data processing system using read-only-memory arrays to provide operation in a plurality of operating states 失效
    • Data processing system using read-only-memory arrays to provide operation in a plurality of operating states
    • 数据处理系统使用只读存储器阵列来提供多个操作状态的操作
    • US4079454A
    • 1978-03-14
    • US737417
    • 1976-11-01
    • Karsten Sorenson , David H. Bernstein , Michael B. Druke
    • Karsten Sorenson , David H. Bernstein , Michael B. Druke
    • G06F1/04 , G06F9/22 , G06F13/18 , G06F13/42 , G06F13/00
    • G06F1/04 , G06F13/18 , G06F13/4243 , G06F9/226
    • A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose.The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an input and an A-input and a B-input.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US08054752B2 Synchronous data communication 有权
    • Synchronous data communication
    • 同步数据通信
    • US08054752B2
    • 2011-11-08
    • US11479203
    • 2006-06-30
    • Michael B. Druke , Christopher J. Jacques
    • Michael B. Druke , Christopher J. Jacques
    • G01R31/08 , G05B19/04
    • H04L47/10 , H04L1/0083 , H04L1/1664 , H04L1/1671 , H04L1/1854 , H04L1/1887 , H04L47/263 , H04L47/35
    • A data packet is provided that includes a synchronization field and an acknowledgement field indicative of an acknowledgement of receipt of a prior data packet. The data packet also includes a response field that includes information indicative of a system fault, a header field, and a sequence number field that includes a number assigned to the data packet. The data packet further includes a data field, an end of packet field, and an error-checking field. Methods and computer program products are provided that, in some implementations, include retransmitting packets if the acknowledgement field in a received data packet is a no acknowledgement (NAK) and/or placing a node into a safe state in response to a fault signal that is included in the received data packet.
    • 提供了包括同步字段和指示接收先前数据分组的确认的确认字段的数据分组。 数据分组还包括包括指示系统故障的信息，报头字段和包括分配给数据分组的编号的序列号字段的响应字段。 数据分组还包括数据字段，分组字段的结束和错误检查字段。 提供了方法和计算机程序产品，在一些实现中，如果接收到的数据分组中的确认字段是无响应（NAK）和/或响应于故障信号将节点置于安全状态，则包括重传分组 包含在接收的数据包中。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US4014006A Data processing system having a unique CPU and memory tuning relationship and data path configuration 失效
    • Data processing system having a unique CPU and memory tuning relationship and data path configuration
    • 具有独特CPU和内存调谐关系和数据路径配置的数据处理系统
    • US4014006A
    • 1977-03-22
    • US646351
    • 1976-01-02
    • Karsten Sorensen , David H. Bernstein , Michael B. Druke
    • Karsten Sorensen , David H. Bernstein , Michael B. Druke
    • G06F1/04 , G06F9/22 , G06F13/42 , G06F13/00
    • G06F13/4243 , G06F1/04 , G06F9/226
    • A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose.The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an output and an A-input and a B-input.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 8. 发明申请
      US20120039162A1 Synchronous Data Communication 有权
    • Synchronous Data Communication
    • 同步数据通信
    • US20120039162A1
    • 2012-02-16
    • US13280150
    • 2011-10-24
    • Michael B. Druke , Christopher J. Jacques
    • Michael B. Druke , Christopher J. Jacques
    • G06F11/00
    • H04L47/10 , H04L1/0083 , H04L1/1664 , H04L1/1671 , H04L1/1854 , H04L1/1887 , H04L47/263 , H04L47/35
    • A data packet is provided that includes a synchronization field and an acknowledgement field indicative of an acknowledgement of receipt of a prior data packet. The data packet also includes a response field that includes information indicative of a system fault, a header field, and a sequence number field that includes a number assigned to the data packet. The data packet further includes a data field, an end of packet field, and an error-checking field. Methods and computer program products are provided that, in some implementations, include retransmitting packets if the acknowledgement field in a received data packet is a no acknowledgement (NAK) and/or placing a node into a safe state in response to a fault signal that is included in the received data packet.
    • 提供了包括同步字段和指示接收先前数据分组的确认的确认字段的数据分组。 数据分组还包括包括指示系统故障的信息，报头字段和包括分配给数据分组的编号的序列号字段的响应字段。 数据分组还包括数据字段，分组字段的结束和错误检查字段。 提供了方法和计算机程序产品，在一些实现中，如果接收到的数据分组中的确认字段是无响应（NAK）和/或响应于故障信号将节点置于安全状态，则包括重传分组 包含在接收的数据包中。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US4736287A Set association memory system 失效
    • Set association memory system
    • 设置关联内存系统
    • US4736287A
    • 1988-04-05
    • US930861
    • 1986-11-14
    • Michael B. Druke , Walter A. Wallach
    • Michael B. Druke , Walter A. Wallach
    • G06F12/08 , G06F12/12 , G06F9/26
    • G06F12/128 , G06F12/0864
    • A memory system for use in a computer which in the preferred embodiment provides two megabytes of capacity per board (up to four boards) is disclosed. An ALU generates an address signal which selects a number of set locations in the main memory. Simultaneously, a portion of the address field is fed to a set association logic circuit for parallel processing. The set association circuit contains tag storage memories and comparators which store tag values. These values are compared with address fields, and if a match occurs, one of the comparators selects a 128-bit word from the main memory. A hash function is also used to provide for dispersal of storage locations to reduce the number of collisions of frequently used addresses. Because of hardware implementation of hashing and least recently used (LRU) algorithm, a constant predetermined cycle time is realized since all accessing functions occur substantially in parallel. Several sets of data are accessed simultaneously while a set association process is performed which selects one of the accessed sets, wherein access time is reduced because of the parallel accessing.
    • 一种在计算机中使用的存储器系统，其在优选实施例中提供了每个板（最多四个板）两兆字节的容量。 ALU产生一个地址信号，该地址信号选择主存储器中的多个设置位置。 同时，地址字段的一部分被馈送到用于并行处理的集合关联逻辑电路。 集合关联电路包含标签存储存储器和存储标签值的比较器。 这些值与地址字段进行比较，如果发生匹配，则比较器中的一个从主存储器中选择128位字。 散列函数也用于提供存储位置的分散以减少频繁使用的地址的冲突次数。 由于哈希算法和最近最少使用的（LRU）算法的硬件实现，实现了恒定的预定周期时间，因为所有访问功能基本上并行发生。 在执行设置的关联处理时，同时访问几组数据，其中，所述集合关联处理选择所访问的集合中的一个，其中由于并行访问而减少访问时间。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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