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1. 发明申请

US20180109266A1 Programmable Clock Divider 审中-公开
公开(公告)号：US20180109266A1
公开(公告)日：2018-04-19
申请号：US15297537
申请日：2016-10-19
申请人： STMicroelectronics International N.V.
发明人： Nitin Gupta , Jeet Narayan Tiwari
IPC分类号： H03L7/197 , H03K19/20
CPC分类号： H03L7/1974 , H03K19/20 , H03K21/00 , H03K21/10 , H03K23/00 , H03K23/667 , H03K23/68 , H03K23/70
摘要： In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.

2. 发明申请

US20170366193A1 PROGRAMMABLE FREQUENCY DIVIDER, PLL SYNTHESIZER AND RADAR DEVICE 审中-公开
公开(公告)号：US20170366193A1
公开(公告)日：2017-12-21
申请号：US15609925
申请日：2017-05-31
申请人： FUJITSU LIMITED
发明人： Hiroshi Matsumura
IPC分类号： H03L7/199 , H03K23/66 , G01S7/02
CPC分类号： H03L7/199 , G01S7/02 , G01S7/03 , G01S7/35 , H03K23/667 , H03L7/1974
摘要： A programmable frequency divider includes a modulus frequency divider, a pulse counter, and a swallow counter. The pulse counter is configured to count an output signal from the modulus frequency divider, and output a frequency division signal, and the swallow counter is configured to count the output signal from the modulus frequency divider and perform resetting on the basis of the frequency division signal from the pulse counter, the programmable frequency divider being configured to control the modulus frequency divider on the basis of a signal from the swallow counter. The programmable frequency divider includes a control signal delay circuit, disposed between an output terminal of the swallow counter and a control terminal of the modulus frequency divider, configured to delay a signal from the swallow counter, and generate a control signal for controlling the modulus frequency divider.

3. 发明授权

US09325541B2 Modular frequency divider with switch configuration to reduce parasitic capacitance 有权
标题翻译：具有开关配置的模块化分频器，以减少寄生电容
公开(公告)号：US09325541B2
公开(公告)日：2016-04-26
申请号：US14279780
申请日：2014-05-16
申请人： Marvell World Trade LTD.
发明人： Alberto Pirola , Danilo Gerna
IPC分类号： H04B1/04 , H04L25/08 , H04L25/03 , H03B19/00 , H03K23/66 , H03K21/10 , H04W52/36
CPC分类号： H04L25/08 , H03B19/00 , H03K21/10 , H03K23/667 , H04L25/03828 , H04W52/367
摘要： A system comprising a first frequency divider to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of a plurality of second frequency dividers divides the input frequency of the input signal to generate a second signal having the first frequency and a second phase. A first switch includes a first end connected to a first node of the first frequency divider, and a second end connected to a second node of a first one of the plurality of second frequency dividers. A plurality of second switches include first ends connected to the second end of the first switch, and second ends respectively connected to the second nodes of the plurality of second frequency dividers other than the first one of the plurality of second frequency dividers.
摘要翻译：一种系统，包括：第一分频器，用于对输入信号的输入频率进行分频，以产生具有第一频率和第一相位的第一信号。多个第二分频器中的每一个分频器将输入信号的输入频率除以产生具有第一频率和第二相位的第二信号。第一开关包括连接到第一分频器的第一节点的第一端和连接到多个第二分频器中的第一分频器的第二节点的第二端。多个第二开关包括连接到第一开关的第二端的第一端和分别连接到多个第二分频器中除第一分频器中的第一分频器之外的多个第二分频器的第二节点的第二端。

4. 发明授权

US09258506B2 Counter circuit, analog-to-digital converter, and image sensor including the same and method of correlated double sampling 有权
标题翻译：计数器电路，模数转换器和图像传感器包括相同的方法和相关的双重采样方法
公开(公告)号：US09258506B2
公开(公告)日：2016-02-09
申请号：US14335309
申请日：2014-07-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Ji-Hun Shin , Chang-Eun Kang , Won-Ho Choi , Dong-Hun Lee
IPC分类号： H04N5/335 , H04N5/378 , H03K21/38 , H03K23/66 , H03M1/14 , H03M1/12 , H03M1/56 , H04N5/357 , H04N5/369 , H04N5/3745 , H04N13/02
CPC分类号： H04N5/378 , H03K21/38 , H03K23/667 , H03M1/123 , H03M1/14 , H03M1/56 , H04N5/3575 , H04N5/3696 , H04N5/3745 , H04N13/243 , H04N13/254 , H04N13/271 , H04N2213/001
摘要： A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.
摘要翻译：计数器电路包括第一计数器和第二计数器。第一计数器被配置为响应于基于第一比较的第一计数使能信号来计数与第一频率切换的第一计数器时钟信号，以产生N位计数器输出信号的上（N-M）位信号信号在粗计数间隔期间。 N和M是自然数，N大于M，M大于或等于3.第二计数器被配置为对第二计数器时钟信号进行计数，第二计数器时钟信号与第二频率相交换，第二频率高于第一频率以产生响应于基于第一比较信号的第二计数使能信号和在粗计数间隔之后的精细计数间隔期间的第二比较信号，N比特计数器输出信号的较低M比特信号。

5. 发明授权

US09118333B1 Self-adaptive multi-modulus dividers containing div2/3 cells therein 有权
标题翻译：在其中包含div2 / 3单元的自适应多模式分频器
公开(公告)号：US09118333B1
公开(公告)日：2015-08-25
申请号：US14013599
申请日：2013-08-29
申请人： Integrated Device Technology, Inc.
发明人： Benedykt Mika , Pengfei Hu
IPC分类号： H03K21/00 , H03K23/00 , H03K23/70 , H03K23/68 , H03K23/66
CPC分类号： H03K23/70 , H03K21/00 , H03K21/023 , H03K21/38 , H03K23/00 , H03K23/667 , H03K23/68
摘要： Integrated circuit devices include programmable dividers, such as fractional-N dividers, which can utilize multi-modulus dividers (MMD) therein. A multi-modulus divider includes a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte P during an update time interval and may even fully turn off one or more of the div2/3 cells not participating in a divide-by-N operation, where N is a positive integer greater than one. The div2/3 cells are configured to include a modulus input terminal and a modulus output terminal and the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.
摘要翻译：集成电路设备包括可以使用其中的多模式分频器（MMD）的可编程分频器，例如分数N分频器。多模式分配器包括一个分级链div2 / 3单元，其被配置为支持链长控制操作，该操作排除在响应于链长度控制字节P 的值的变化期间产生中间除数更新时间间隔，甚至可以完全关闭不参与除N运算的一个或多个div2 / 3单元，其中N是大于1的正整数。 div2 / 3单元被配置为包括模数输入端和模输出端，并且链长控制操作与提供给div2 / 3单元的模输入端的信号的幅度无关。

6. 发明申请

US20150091620A1 REDUCING CURRENT VARIATION WHEN SWITCHING CLOCKS 审中-公开
标题翻译：切换时钟时减少电流变化
公开(公告)号：US20150091620A1
公开(公告)日：2015-04-02
申请号：US14045295
申请日：2013-10-03
申请人： LSI Corporation
发明人： Steven J. Pollock
IPC分类号： H03K17/16
CPC分类号： H03K23/667
摘要： An apparatus includes a glitchless divider and a glitchless multiplexer. The glitchless divider may be configured to generate a first system clock in response to a divider value and a clock signal received from a first source. The divider value changes from a first value to a second value in a predetermined number of steps. The glitchless multiplexer may be configured to select between said first system clock and a second system clock in response to a control signal.
摘要翻译：一种装置包括无毛刺分频器和无毛刺多路复用器。无毛刺除法器可以被配置为响应于从第一源接收的分频器值和时钟信号而产生第一系统时钟。分频值以预定的步数从第一值改变到第二值。无毛刺多路复用器可以被配置为响应于控制信号在所述第一系统时钟和第二系统时钟之间进行选择。

7. 发明申请

US20150028190A1 COUNTER CIRCUIT, ANALOG-TO-DIGITAL CONVERTER, AND IMAGE SENSOR INCLUDING THE SAME AND METHOD OF CORRELATED DOUBLE SAMPLING 有权
标题翻译：计数器电路，模拟数字转换器和包括它们的图像传感器和相关双重采样方法
公开(公告)号：US20150028190A1
公开(公告)日：2015-01-29
申请号：US14335309
申请日：2014-07-18
申请人： Ji-Hun SHIN , Chang-Eun KANG , Won-Ho CHOI , Dong-Hun LEE
发明人： Ji-Hun SHIN , Chang-Eun KANG , Won-Ho CHOI , Dong-Hun LEE
IPC分类号： H03M1/00 , H04N5/378 , H03K3/356 , H03K23/00 , H03M1/12
CPC分类号： H04N5/378 , H03K21/38 , H03K23/667 , H03M1/123 , H03M1/14 , H03M1/56 , H04N5/3575 , H04N5/3696 , H04N5/3745 , H04N13/243 , H04N13/254 , H04N13/271 , H04N2213/001
摘要： A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.
摘要翻译：计数器电路包括第一计数器和第二计数器。第一计数器被配置为响应于基于第一比较的第一计数使能信号来计数与第一频率切换的第一计数器时钟信号，以产生N位计数器输出信号的上（N-M）位信号信号在粗计数间隔期间。 N和M是自然数，N大于M，M大于或等于3.第二计数器被配置为对第二计数器时钟信号进行计数，第二计数器时钟信号与第二频率相交换，第二频率高于第一频率以产生响应于基于第一比较信号的第二计数使能信号和在粗计数间隔之后的精细计数间隔期间的第二比较信号，N比特计数器输出信号的较低M比特信号。

8. 发明申请

US20140247903A1 MODULAR FREQUENCY DIVIDER WITH SWITCH CONFIGURATION TO REDUCE PARASITIC CAPACITANCE 有权
标题翻译：具有开关配置的模块化分频器以降低PARASIIC电容
公开(公告)号：US20140247903A1
公开(公告)日：2014-09-04
申请号：US14279780
申请日：2014-05-16
申请人： Marvell World Trade LTD.
发明人： Alberto Pirola , Danilo Gerna
IPC分类号： H04L25/08 , H04L25/03
CPC分类号： H04L25/08 , H03B19/00 , H03K21/10 , H03K23/667 , H04L25/03828 , H04W52/367
摘要： A system comprising a first frequency divider to divide an input frequency of an input signal to generate a first signal having a first frequency and a first phase. Each of a plurality of second frequency dividers divides the input frequency of the input signal to generate a second signal having the first frequency and a second phase. A first switch includes a first end connected to a first node of the first frequency divider, and a second end connected to a second node of a first one of the plurality of second frequency dividers. A plurality of second switches include first ends connected to the second end of the first switch, and second ends respectively connected to the second nodes of the plurality of second frequency dividers other than the first one of the plurality of second frequency dividers.
摘要翻译：一种系统，包括：第一分频器，用于对输入信号的输入频率进行分频，以产生具有第一频率和第一相位的第一信号。多个第二分频器中的每一个分频器将输入信号的输入频率除以产生具有第一频率和第二相位的第二信号。第一开关包括连接到第一分频器的第一节点的第一端和连接到多个第二分频器中的第一分频器的第二节点的第二端。多个第二开关包括连接到第一开关的第二端的第一端和分别连接到多个第二分频器中除第一分频器中的第一分频器之外的多个第二分频器的第二节点的第二端。

9. 发明授权

US08786325B2 Integrated circuit chip and system having the same 有权
公开(公告)号：US08786325B2
公开(公告)日：2014-07-22
申请号：US14145489
申请日：2013-12-31
申请人： SK hynix Inc.
发明人： Seung-Min Oh
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： G11C7/1066 , H03K23/667
摘要： An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

10. 发明授权

US08633739B2 Frequency divider circuit 有权
标题翻译：分频器电路
公开(公告)号：US08633739B2
公开(公告)日：2014-01-21
申请号：US13169994
申请日：2011-06-27
申请人： Dean A. Badillo
发明人： Dean A. Badillo
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K23/667 , H03K23/68
摘要： Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle.
摘要翻译：通过依次选择用于除法的相位信号进行分数分频，其中不仅响应于分频的前一相位信号，而且响应于相位信号中的第二相位信号，从而从先前相位信号转换到下一相位信号进行分频。至少部分响应于具有相对于下一个相位信号的相位较大的相位（相对于相位信号序列）的相位的第二相位信号触发的相位转移可以帮助信号毛刺的最小化。可以将第一分频信号进一步分割以产生具有50％占空比的第二分频信号。

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