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1. 发明授权

US09344080B1 Dual-gate transistor control based on calibration circuitry 有权
标题翻译：基于校准电路的双栅晶体管控制
公开(公告)号：US09344080B1
公开(公告)日：2016-05-17
申请号：US14667069
申请日：2015-03-24
申请人： Michael C. Stephens, Jr.
发明人： Michael C. Stephens, Jr.
IPC分类号： H03K17/296 , H03K17/284 , H03K17/30 , H03K17/687
CPC分类号： H03K17/284 , G05F1/468 , G11C7/065 , G11C7/08 , G11C7/22 , G11C29/026 , G11C29/028 , H03K17/302 , H03K17/687 , H03K17/6871 , H03K2017/6878
摘要： Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.
摘要翻译：公开了与双栅极晶体管和相关联的校准电路相关的各种实施例。在一个实施例中，双栅极晶体管可以配置在读出放大器布置中，并且校准电路可用于调整读出放大器的输入偏移。在另一个实施例中，在具有双栅极晶体管的放大器中使用的参考电平电压可以在校准序列期间被调整，并且可以在校准序列之外的标称值基本上不变。在另一个实施例中，可利用校准序列来确定来自包括双栅极晶体管的电路的电路结果，并且将控制栅极调整为更接近于预期或期望的结果。在另一个实施例中，半导体存储器件可以包括具有包括双栅极晶体管的放大器以及相关联的校准电路的存储器阵列。

2. 发明授权

US09286955B1 Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array 有权
公开(公告)号：US09286955B1
公开(公告)日：2016-03-15
申请号：US14668863
申请日：2015-03-25
申请人： Michael C. Stephens, Jr.
发明人： Michael C. Stephens, Jr.
IPC分类号： G11C7/00 , G11C7/08 , G11C7/06 , G11C7/22
CPC分类号： H03K17/284 , G05F1/468 , G11C7/065 , G11C7/08 , G11C7/22 , G11C29/026 , G11C29/028 , H03K17/302 , H03K17/687 , H03K17/6871 , H03K2017/6878
摘要： Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.

3. 发明授权

US09153298B2 Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements 有权
标题翻译：基于堆叠排列的存储器件中的堆栈位置标识符的延迟调整
公开(公告)号：US09153298B2
公开(公告)日：2015-10-06
申请号：US13534279
申请日：2012-06-27
申请人： Michael C. Stephens, Jr.
发明人： Michael C. Stephens, Jr.
IPC分类号： G11C5/06 , G11C7/10 , G11C11/406 , G11C5/04 , G11C29/02 , G11C29/50 , G11C5/14 , G11C16/30 , G11C5/02 , G11C11/401 , G11C29/44 , G11C7/22
CPC分类号： G11C11/4076 , G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/14 , G11C5/147 , G11C7/10 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4093 , G11C11/4094 , G11C15/00 , G11C16/30 , G11C29/023 , G11C29/028 , G11C29/50016 , G11C2029/4402 , G11C2211/4061 , G11C2211/4067 , G11C2213/71 , H01L2224/16145
摘要： Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
摘要翻译：公开了与层叠存储器件（例如DRAM，SRAM，EEPROM，ReRAM和CAM）相关的各种实施例。例如，堆栈位置标识符（SPID）被分配或以其他方式确定，并且被每个存储器设备用于进行多个调整。在一个实施例中，基于该设备的SPID来调整DRAM的自刷新率。在另一实施例中，基于SPID调整DRAM或SRAM的等待时间。在另一个实施例中，内部调节信号通过TSV与其他设备共享。在另一个实施例中，基于特定设备的SPID进行对内部调节信号的调整。在另一个实施例中，可以基于芯片SPID（例如，偶数或奇数堆栈位置）来控制串行连接的信号，以及该信号是上游还是下游信号。

4. 发明授权

US08659928B1 Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements 有权
标题翻译：基于堆叠排列的存储器件中的堆栈位置标识符进行有效的命令检测
公开(公告)号：US08659928B1
公开(公告)日：2014-02-25
申请号：US13491090
申请日：2012-06-07
申请人： Michael C. Stephens, Jr.
发明人： Michael C. Stephens, Jr.
IPC分类号： G11C5/06
CPC分类号： G11C11/4076 , G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/14 , G11C5/147 , G11C7/10 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4093 , G11C11/4094 , G11C15/00 , G11C16/30 , G11C29/023 , G11C29/028 , G11C29/50016 , G11C2029/4402 , G11C2211/4061 , G11C2211/4067 , G11C2213/71 , H01L2224/16145
摘要： Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
摘要翻译：公开了与层叠存储器件（例如DRAM，SRAM，EEPROM，ReRAM和CAM）相关的各种实施例。例如，堆栈位置标识符（SPID）被分配或以其他方式确定，并且被每个存储器设备用于进行多个调整。在一个实施例中，基于该设备的SPID来调整DRAM的自刷新率。在另一实施例中，基于SPID调整DRAM或SRAM的等待时间。在另一个实施例中，内部调节信号通过TSV与其他设备共享。在另一个实施例中，基于特定设备的SPID进行对内部调节信号的调整。在另一个实施例中，可以基于芯片SPID（例如，偶数或奇数堆栈位置）来控制串行连接的信号，以及该信号是上游还是下游信号。

5. 发明授权

US08614909B1 Internal supply testing in memory devices configured for stacked arrangements 有权
标题翻译：存储器件中的内部电源测试配置为堆叠布置
公开(公告)号：US08614909B1
公开(公告)日：2013-12-24
申请号：US13466736
申请日：2012-05-08
申请人： Michael C. Stephens, Jr.
发明人： Michael C. Stephens, Jr.
IPC分类号： G11C5/06 , G11C5/02 , H01L23/02 , H01L23/12 , H01L23/52
CPC分类号： G11C11/4076 , G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/14 , G11C5/147 , G11C7/10 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4093 , G11C11/4094 , G11C15/00 , G11C16/30 , G11C29/023 , G11C29/028 , G11C29/50016 , G11C2029/4402 , G11C2211/4061 , G11C2211/4067 , G11C2213/71 , H01L2224/16145
摘要： Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
摘要翻译：公开了与层叠存储器件（例如DRAM，SRAM，EEPROM，ReRAM和CAM）相关的各种实施例。例如，堆栈位置标识符（SPID）被分配或以其他方式确定，并且被每个存储器设备用于进行多个调整。在一个实施例中，基于该设备的SPID来调整DRAM的自刷新率。在另一实施例中，基于SPID调整DRAM或SRAM的等待时间。在另一个实施例中，内部调节信号通过TSV与其他设备共享。在另一个实施例中，基于特定设备的SPID进行对内部调节信号的调整。在另一个实施例中，可以基于芯片SPID（例如，偶数或奇数堆栈位置）来控制串行连接的信号，以及该信号是上游还是下游信号。

6. 发明授权

US06764867B1 Reticle option layer detection method 有权
标题翻译：掩模选项层检测方法
公开(公告)号：US06764867B1
公开(公告)日：2004-07-20
申请号：US09764243
申请日：2001-01-19
申请人： Michael C. Stephens, Jr. , Christopher Ematrudo , Jeffrey S. Earl
发明人： Michael C. Stephens, Jr. , Christopher Ematrudo , Jeffrey S. Earl
IPC分类号： H01L2100
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/3011
摘要： A new method of detecting a reticle option layer in an integrated circuit device has been achieved. The method may be applied to detect the presence of the threshold voltage implantation reticle option layer by direct die probing or by probing a pin of a package integrated circuit. The current through a first MOS transistor is measured by forcing a test voltage on the drain and the gate. The gate and the drain of the first MOS transistor are connected together while the source is connected to a reference voltage. The first MOS transistor has the standard threshold implantation but not the threshold voltage reticle option. The current through a second MOS transistor is measured by forcing the same test voltage on the drain and the gate. The gate and said drain of the second MOS transistor are connected together while the source is connected to a reference voltage. The second MOS transistor has the standard threshold voltage implantation and the threshold voltage implantation reticle option layer. The current through the first NMOS transistor and the current through the second MOS transistor are compared to detect the presence of the threshold voltage implantation reticle option layer in the integrated circuit device.
摘要翻译：已经实现了在集成电路装置中检测掩模版选择层的新方法。该方法可以用于通过直接芯片探测或通过探测封装集成电路的引脚来检测阈值电压注入掩模版选择层的存在。通过在漏极和栅极上施加测试电压来测量通过第一MOS晶体管的电流。第一MOS晶体管的栅极和漏极连接在一起，同时源极连接到参考电压。第一个MOS晶体管具有标准阈值植入，但不是阈值电压掩模版选项。通过第二MOS晶体管的电流通过在漏极和栅极上施加相同的测试电压来测量。第二MOS晶体管的栅极和漏极连接在一起，同时源极连接到参考电压。第二MOS晶体管具有标准阈值电压注入和阈值电压注入掩模版选择层。比较通过第一NMOS晶体管的电流和通过第二MOS晶体管的电流，以检测集成电路器件中阈值电压注入掩模版选项层的存在。

7. 发明授权

US6016072A Regulator system for an on-chip supply voltage generator 失效
标题翻译：用于片内电源电压发生器的调节器系统
公开(公告)号：US6016072A
公开(公告)日：2000-01-18
申请号：US46408
申请日：1998-03-23
申请人： Luigi Ternullo, Jr. , Michael C. Stephens
发明人： Luigi Ternullo, Jr. , Michael C. Stephens
IPC分类号： H02M3/07 , G05F1/10
CPC分类号： H02M3/07
摘要： A regulator system includes first and second voltage sensing circuits coupled to a voltage generator control circuit. The first and second voltage sensing circuits are configured to monitor the voltage generated by the on-chip voltage generator (i.e., the on-chip supply voltage) and detect when the on-chip supply voltage reaches thresholds that are predetermined to define a desired range of the on-chip supply voltage. The voltage generator control circuit receives voltage sense signals from the voltage sense circuits and, in response, asserts or de-asserts a control signal received by the on-chip voltage generator so as to activate or de-activate the on-chip voltage generator to maintain the on-chip supply voltage within the desired range. The voltage generator control circuit introduces hysteresis in the generation of the control signal provided to the on-chip voltage generator. As a result of this hysteresis, once the on-chip voltage generator is activated, the voltage generator control circuit only de-activates the on-chip voltage generator when the on-chip supply voltage reaches the higher threshold. Conversely, once the on-chip voltage generator is de-activated, the voltage generator control circuit only activates the on-chip voltage generator when the on-chip supply voltage reaches the lower threshold.
摘要翻译：调节器系统包括耦合到电压发生器控制电路的第一和第二电压感测电路。第一和第二电压感测电路被配置为监视片上电压发生器产生的电压（即，片上电源电压），并且检测片上电源电压何时达到预定的阈值以限定期望的范围的片上电源电压。电压发生器控制电路接收来自电压检测电路的电压检测信号，并作为响应，断言或取消断言由片上电压发生器接收的控制信号，以激活或去激活片上电压发生器将片上电源电压保持在所需范围内。电压发生器控制电路在提供给片上电压发生器的控制信号的产生中引入滞后。作为这种滞后的结果，一旦芯片上的电压发生器被激活，当片上电源电压达到较高的阈值时，电压发生器控制电路仅仅去激活片上电压发生器。相反，一旦片上电压发生器被去激活，当片上电源电压达到较低阈值时，电压发生器控制电路仅激活片上电压发生器。

8. 发明授权

US5550783A Phase shift correction circuit for monolithic random access memory 失效
标题翻译：单片随机存取存储器的相移校正电路
公开(公告)号：US5550783A
公开(公告)日：1996-08-27
申请号：US424820
申请日：1995-04-19
申请人： Michael C. Stephens, Jr. , Ajit K. Medhekar
发明人： Michael C. Stephens, Jr. , Ajit K. Medhekar
IPC分类号： G11C7/22 , G11C8/00
CPC分类号： G11C7/225 , G11C7/22
摘要： A synchronous burst SRAM (110) is disclosed that includes a clock circuit (112) having a phase correction subcircuit (134) and a clock routing subcircuit (132). The clock routing subcircuit (132) provides an internal clock signal to at least one clocked circuit. The phase correction subcircuit (134) is a modified phase locked loop that includes a phase comparator (138) that receives an external clock signal and a delayed internal clock signal. In response to the signals, the phase comparator (138) provides a phase error signal to a charge pump (140) which is coupled to a loop filter (142) to provide an error voltage. The error voltage is coupled to a VCO (144) which provides the internal clock signal as an output. The internal clock signal is coupled to the input of the phase comparator (138) by a feedback circuit which generates the delayed internal clock signal for the phase comparator (138). The feedback circuit can include a number of delay elements (146) to simulate the clock delay inherent in the clock routing subcircuit (132) so that the resulting internal clock signal is phase shifted to compensate for delays caused by the clock routing subcircuit (132).
摘要翻译：公开了一种同步突发SRAM（110），其包括具有相位校正子电路（134）和时钟路由子电路（132）的时钟电路（112）。时钟路由分支电路（132）向至少一个时钟电路提供内部时钟信号。相位校正子电路（134）是修改的锁相环，其包括接收外部时钟信号和延迟的内部时钟信号的相位比较器（138）。响应于信号，相位比较器（138）向电荷泵（140）提供相位误差信号，电荷泵（140）耦合到环路滤波器（142）以提供误差电压。误差电压耦合到提供内部时钟信号作为输出的VCO（144）。内部时钟信号通过产生相位比较器（138）的延迟的内部时钟信号的反馈电路耦合到相位比较器（138）的输入端。反馈电路可以包括多个延迟元件（146），以模拟时钟路由子电路（132）中固有的时钟延迟，使得所得到的内部时钟信号相移以补偿由时钟路由子电路（132）引起的延迟，。

9. 发明授权

US5550500A Timing delay modulation scheme for integrated circuits 失效
标题翻译：集成电路定时延时调制方案
公开(公告)号：US5550500A
公开(公告)日：1996-08-27
申请号：US493901
申请日：1995-06-23
申请人： Michael C. Stephens, Jr. , Ajit K. Medhekar
发明人： Michael C. Stephens, Jr. , Ajit K. Medhekar
IPC分类号： H03K5/13 , H03K5/153
CPC分类号： H03K5/131 , H03K5/133
摘要： A timing delay modulation scheme for integrated circuits (10) is disclosed. A super voltage is applied to existing bond pads (30) and detected by super voltage detect circuits (34) which generate a number of logic input signals (22) to a logic unit (18). In response, the logic unit (18) provides a number of control signals (24) which are coupled to timing adjust circuits (20). In the preferred embodiment, in response to its respective control signals, each timing adjust circuit (20) pushes-out or pulls-in, a separate internal timing signal (S0-S3) of the integrated circuit. The super voltage detect circuit (34) includes an adjustable effective super voltage level, and is capable of being disabled. Further, the timing adjustment provided by each timing adjust circuit (20) can be altered.
摘要翻译：公开了一种用于集成电路（10）的定时延迟调制方案。超电压被施加到现有的接合焊盘（30）上，并由产生多个逻辑输入信号（22）的逻辑单元（18）的超电压检测电路（34）检测。作为响应，逻辑单元（18）提供耦合到定时调节电路（20）的多个控制信号（24）。在优选实施例中，响应于其各自的控制信号，每个定时调整电路（20）将集成电路的单独的内部定时信号（S0-S3）推出或拉入。超级电压检测电路（34）包括可调节的有效超级电平，并且能够被禁用。此外，可以改变由每个定时调整电路（20）提供的定时调整。

10. 发明授权

US09601167B1 Semiconductor device having dual-gate transistors and calibration circuitry 有权
公开(公告)号：US09601167B1
公开(公告)日：2017-03-21
申请号：US14665711
申请日：2015-03-23
申请人： Michael C. Stephens, Jr.
发明人： Michael C. Stephens, Jr.
IPC分类号： G11C7/08 , G11C7/06
CPC分类号： H03K17/284 , G05F1/468 , G11C7/065 , G11C7/08 , G11C7/22 , G11C29/026 , G11C29/028 , H03K17/302 , H03K17/687 , H03K17/6871 , H03K2017/6878
摘要： Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.

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