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1. 发明申请

US20110216569A1 CONTENT ADDRESSABLE MEMORY DEVICE 有权
标题翻译：内容可寻址存储器件
公开(公告)号：US20110216569A1
公开(公告)日：2011-09-08
申请号：US13038916
申请日：2011-03-02
申请人： Mihoko AKIYAMA
发明人： Mihoko AKIYAMA
IPC分类号： G11C15/00
CPC分类号： G11C5/14 , G11C15/00 , G11C15/04
摘要： A content addressable memory device capable of making simultaneous pursuit of low power consumption and speeding up is provided. A match amplifier A determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array A, according to a voltage of a match line MLA. A match amplifier B determines coincidence or non-coincidence of search data and data stored in a content addressable memory in an entry of a memory array B, according to a voltage of a match line MLB. A block-B control circuit directs to start searching in the memory array B after two cycles after searching has been started in the memory array A. A block-B activation control circuit directs to stop searching in the memory array B according to a voltage of the match line MLA after searching in the memory array A.
摘要翻译：提供了能够同时追求低功耗和加速的内容可寻址存储装置。匹配放大器A根据匹配线MLA的电压，确定存储器阵列A的条目中存储在内容可寻址存储器中的搜索数据和数据的一致或非重合。匹配放大器B根据匹配线MLB的电压确定搜索数据和存储在存储器阵列B的条目中的内容可寻址存储器中的数据的一致或非重合。块B控制电路指示在存储器阵列A中开始搜索之后的两个周期之后在存储器阵列B中开始搜索。块B激活控制电路指示根据存储器阵列B的电压停止在存储器阵列B中的搜索在存储器阵列A中搜索后的匹配线MLA。

2. 发明授权

US07656736B2 Semiconductor device including internal voltage generation circuit 有权
标题翻译：半导体器件包括内部电压产生电路
公开(公告)号：US07656736B2
公开(公告)日：2010-02-02
申请号：US11717717
申请日：2007-03-14
申请人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
发明人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC分类号： G11C5/14
CPC分类号： G05F1/468 , G11C5/025 , G11C5/147
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译：半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。因此，相对于负电压的变化的响应增加。在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路活性。因此，可以防止待机电流的增加。

3. 发明申请

US20070247885A1 Content addressable memory 审中-公开
标题翻译：内容可寻址内存
公开(公告)号：US20070247885A1
公开(公告)日：2007-10-25
申请号：US11730969
申请日：2007-04-05
申请人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
IPC分类号： G11C15/00
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译：包括存储数据位的单位单元的多个比特的条目耦合到匹配线。匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流。匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

4. 发明授权

US07023754B2 Semiconductor device having standby mode and active mode 失效
标题翻译：具有待机模式和活动模式的半导体器件
公开(公告)号：US07023754B2
公开(公告)日：2006-04-04
申请号：US10279069
申请日：2002-10-24
申请人： Mihoko Akiyama , Fukashi Morishita
发明人： Mihoko Akiyama , Fukashi Morishita
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/065 , G11C11/4074 , G11C2207/2227 , H01L27/0214 , H01L27/10897
摘要： An internal potential generation circuit of an SDRAM includes a standby VDDS generation circuit which has a relatively low current driving force and which generates an internal power supply potential, and an active VDDS generation circuit which has a relatively high current driving force, which is activated during a period after an external power supply potential is applied until a negative potential reaches a threshold potential, and in an activation period, and which generates the internal power supply potential. Therefore, it is possible to raise the internal power supply potential stably without increasing standby current when the power supply is turned on.
摘要翻译： SDRAM的内部电位产生电路包括具有相对低的电流驱动力并产生内部电源电位的备用VDDS生成电路，以及具有相对高的电流驱动力的有源VDDS生成电路，其在在施加外部电源电位直到负电位达到阈值电位并且在激活时段内产生内部电源电位的时间段。因此，可以在电源接通时不增加待机电流而稳定地提高内部电源电位。

5. 发明授权

US06700434B2 Substrate bias voltage generating circuit 失效
标题翻译：基板偏压生成电路
公开(公告)号：US06700434B2
公开(公告)日：2004-03-02
申请号：US09879914
申请日：2001-06-14
申请人： Nobuyuki Fujii , Fukashi Morishita , Mihoko Akiyama , Akira Yamazaki , Mako Kobayashi , Yasuhiko Taito
发明人： Nobuyuki Fujii , Fukashi Morishita , Mihoko Akiyama , Akira Yamazaki , Mako Kobayashi , Yasuhiko Taito
IPC分类号： G05F1575
CPC分类号： G05F3/205 , H03K3/0315 , H03K3/354
摘要： Oscillation outputs which are different for respective detector signals output from a first detector circuit and a second detector circuit, are obtained from a first ring oscillator and a second ring oscillator respectively corresponding to the detector circuits. A selector selects and outputs one of the oscillation outputs. Accordingly, it is sufficient to provide only one pump circuit in a circuit producing a substrate bias voltage.
摘要翻译：从分别对应于检测器电路的第一环形振荡器和第二环形振荡器获得对从第一检测器电路和第二检测器电路输出的相应检测器信号不同的振荡输出。选择器选择并输出其中一个振荡输出。因此，在产生衬底偏置电压的电路中仅提供一个泵电路就足够了。

6. 发明授权

US06424579B1 Semiconductor memory device with internal power supply potential generation circuit 失效
标题翻译：具有内部电源电位生成电路的半导体存储器件
公开(公告)号：US06424579B1
公开(公告)日：2002-07-23
申请号：US09827897
申请日：2001-04-09
申请人： Mihoko Akiyama , Akira Yamazaki , Fukashi Morishita , Yasuhiko Taito , Nobuyuki Fujii , Mako Okamoto
发明人： Mihoko Akiyama , Akira Yamazaki , Fukashi Morishita , Yasuhiko Taito , Nobuyuki Fujii , Mako Okamoto
IPC分类号： G11C700
CPC分类号： G11C5/147
摘要： In an eDRAM, there are provided a VDC that down-converts an external power supply potential to generate an internal power supply potential for a sense amplifier band, and a VDC that down-converts the external power supply potential to generate an internal power supply potential for a column decoder. The response of the VDC is improved by increasing the through current of the VDC only during the period of time corresponding to an amplify operation of the sense amplifier. Therefore, current consumption is smaller than the conventional case where the through current of the VDC is set at a high constant level.
摘要翻译：在eDRAM中，提供了一个VDC，其降低转换外部电源电位以产生用于读出放大器频带的内部电源电位;以及VDC，其降低转换外部电源电位以产生内部电源电位用于列解码器。通过仅在对应于读出放大器的放大操作的时间段期间增加VDC的通过电流来提高VDC的响应。因此，电流消耗小于将VDC的通电电流设定为高恒定电平的常规情况。

7. 发明授权

US08638583B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08638583B2
公开(公告)日：2014-01-28
申请号：US13621078
申请日：2012-09-15
申请人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
发明人： Naoya Watanabe , Isamu Hayashi , Teruhiko Amano , Fukashi Morishita , Kenji Yoshinaga , Mihoko Akiyama , Shinya Miyazaki , Masakazu Ishibashi , Katsumi Dosaka
IPC分类号： G11C15/00 , G11C15/04 , G11C7/14 , G11C7/06 , G11C7/12 , G11C7/22
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译：包括存储数据位的单位单元的多个比特的条目耦合到匹配线。匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流。匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

8. 发明申请

US20120170344A1 CONTENT ADDRESSABLE MEMORY 有权
标题翻译：内容可寻址内存
公开(公告)号：US20120170344A1
公开(公告)日：2012-07-05
申请号：US13419217
申请日：2012-03-13
申请人： Naoya WATANABE , Isamu HAYASHI , Teruhiko AMANO , Fukashi MORISHITA , Kenji YOSHINAGA , Mihoko AKIYAMA , Shinya MIYAZAKI , Masakazu ISHIBASHI , Katsumi DOSAKA
发明人： Naoya WATANABE , Isamu HAYASHI , Teruhiko AMANO , Fukashi MORISHITA , Kenji YOSHINAGA , Mihoko AKIYAMA , Shinya MIYAZAKI , Masakazu ISHIBASHI , Katsumi DOSAKA
IPC分类号： G11C15/00
CPC分类号： G11C15/043 , G11C7/06 , G11C7/12 , G11C7/14 , G11C7/22 , G11C15/04 , G11C15/046
摘要： An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
摘要翻译：包括存储数据位的单位单元的多个比特的条目耦合到匹配线。匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流。匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

9. 发明授权

US08004923B2 Semiconductor device including internal voltage generation circuit 失效
标题翻译：半导体器件包括内部电压产生电路
公开(公告)号：US08004923B2
公开(公告)日：2011-08-23
申请号：US12683838
申请日：2010-01-07
申请人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
发明人： Mihoko Akiyama , Futoshi Igaue , Kenji Yoshinaga , Masashi Matsumura , Fukashi Morishita
IPC分类号： G11C5/14
CPC分类号： G05F1/468 , G11C5/025 , G11C5/147
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译：半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。因此，相对于负电压的变化的响应增加。在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路活性。因此，可以防止待机电流的增加。

10. 发明授权

US06781431B2 Clock generating circuit 失效
标题翻译：时钟发生电路
公开(公告)号：US06781431B2
公开(公告)日：2004-08-24
申请号：US10349033
申请日：2003-01-23
申请人： Yasuhiko Taito , Akira Yamazaki , Fukashi Morishita , Nobuyuki Fujii , Mihoko Akiyama , Mako Okamoto
发明人： Yasuhiko Taito , Akira Yamazaki , Fukashi Morishita , Nobuyuki Fujii , Mihoko Akiyama , Mako Okamoto
IPC分类号： G06F104
CPC分类号： H03K3/0315 , H02M3/07 , H03K3/013 , H03K3/70
摘要： The clock-generating circuit for generating a clock signal, includes a ring oscillator having an odd number of inverters connected in a ring configuration. The ring oscillator is activated to generate a clock signal when an activating signal is at a first level and is de-activated to cease generation of the clock signal when the activating signal is at a second level. A latch circuit is connected to an output node of the ring oscillator, and holds a level of the output node of the ring oscillator in response to transition of the activating signal from the first level to the second level. When the activating signal is lowered from the H level to the L level, the level of the clock signal is latched such that generation of a glitch in the clock signal will be prevented from occurring.
摘要翻译：用于产生时钟信号的时钟发生电路包括具有以环形配置连接的奇数个反相器的环形振荡器。当激活信号处于第一电平时，环形振荡器被激活以产生时钟信号，并且当激活信号处于第二电平时被停止产生时钟信号。锁存电路连接到环形振荡器的输出节点，并且响应于激活信号从第一电平到第二电平的转变而保持环形振荡器的输出节点的电平。当激活信号从H电平降低到L电平时，锁存时钟信号的电平，从而防止产生时钟信号中的毛刺。

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