专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07671627B1 Superscale processor performance enhancement through reliable dynamic clock frequency tuning 有权
标题翻译：通过可靠的动态时钟频率调谐实现超级处理器性能的提升
公开(公告)号：US07671627B1
公开(公告)日：2010-03-02
申请号：US12107415
申请日：2008-04-22
申请人： Arun Somani , Mikel Bezdek
发明人： Arun Somani , Mikel Bezdek
IPC分类号： H03K19/173
CPC分类号： G06F11/1407 , G06F9/3861 , G06F9/3869 , G06F11/1497 , G06F11/1608
摘要： In the case of a pipelined processor, a performance gain is achievable through dynamically generating a main clock signal associated with a synchronous logic circuit and generating at least one backup register clock signal, the backup register clock signal at the same frequency as the main clock signal and phase shifted from the main clock signal to thereby provide additional time for one or more of the logic stages to execute. Error detection or error recovery may be performed using the backup registers. The methodology can further be extended, to design a system with cheaper technology and simple design tools that initially operates at slower speed, and then dynamically overclocks itself to achieve improved performance, while guaranteeing reliable execution.
摘要翻译：在流水线处理器的情况下，可以通过动态地产生与同步逻辑电路相关联的主时钟信号并产生至少一个备用寄存器时钟信号来实现性能增益，备用寄存器时钟信号与主时钟信号处于相同的频率并从主时钟信号相移，从而为一个或多个逻辑级执行提供额外的时间。可以使用备份寄存器执行错误检测或错误恢复。该方法可以进一步扩展，设计一种具有更低成本的技术和简单的设计工具的系统，它们最初以较慢的速度运行，然后动态超频自身以实现改进的性能，同时保证可靠的执行。

IPRDB

热门服务

关于我们

友情链接

联系方式