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1. 发明授权

US07509568B2 Error type identification circuit for identifying different types of errors in communications devices 失效
标题翻译：用于识别通信设备中不同类型错误的错误类型识别电路
公开(公告)号：US07509568B2
公开(公告)日：2009-03-24
申请号：US11033077
申请日：2005-01-11
申请人： Mohit Kapur , Jose A. Tierno
发明人： Mohit Kapur , Jose A. Tierno
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： An apparatus, method, and computer program product to identify types of errors that occur in a communications device under test and where only the presence of an error is indicated by an error checker. Each presence of an error bit in an error signal during a first period of time output from the error data checker is identified. The error bit indicates only that a mismatch occurred between an input signal input into the device and an output signal output from the device. The error bit is generated in response to an error in the device under test. The error bit includes no information about a type of the error. The type of the error is determined by determining a number of occurrences of the error bit in the error signal during the first period of time.
摘要翻译：一种用于识别发生在被测通信设备中的错误类型的装置，方法和计算机程序产品，并且其中只有错误检查器指示错误的存在。识别在从错误数据检查器输出的第一时间周期内存在错误信号中的错误位的每一个。误差位仅指示输入到器件的输入信号与从器件输出的输出信号之间发生不匹配。响应于被测设备中的错误而产生错误位。错误位不包含有关错误类型的信息。误差的类型通过确定在第一时间段期间误差信号中出现的错误位数来确定。

2. 发明授权

US07177775B2 Testable digital delay line 失效
公开(公告)号：US07177775B2
公开(公告)日：2007-02-13
申请号：US11117924
申请日：2005-04-29
申请人： Mohit Kapur , Seongwon Kim
发明人： Mohit Kapur , Seongwon Kim
IPC分类号： G06F3/02
CPC分类号： G01R31/31725 , H03K2005/00039 , H03K2005/00156
摘要： A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.

3. 发明申请

US20050050419A1 Self-synchronizing pseudorandom bit sequence checker 有权
标题翻译：自同步伪随机比特序列检验器
公开(公告)号：US20050050419A1
公开(公告)日：2005-03-03
申请号：US10650222
申请日：2003-08-28
申请人： Mohit Kapur , Seongwon Kim
发明人： Mohit Kapur , Seongwon Kim
IPC分类号： G01R31/28 , H04L1/20 , H04L1/24
CPC分类号： H04L1/242
摘要： Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.
摘要翻译：提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。在本发明的一个方面，PRBS检查技术包括以下步骤/操作。对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。然后，错误位的传播在后续的时钟周期被禁止。禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

4. 发明授权

US09002693B2 Wire like link for cycle reproducible and cycle accurate hardware accelerator 有权
标题翻译：线条链接循环可再现和循环精确的硬件加速器
公开(公告)号：US09002693B2
公开(公告)日：2015-04-07
申请号：US13342128
申请日：2012-01-02
申请人： Sameh Asaad , Mohit Kapur , Benjamin D. Parker
发明人： Sameh Asaad , Mohit Kapur , Benjamin D. Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.
摘要翻译：提供了第一和第二现场可编程门阵列，其实现要被模拟的电路设计的第一和第二块。现场可编程门阵列以第一时钟频率操作，并且提供线状链路以在它们之间发送多个信号。线状链路包括在第一现场可编程门阵列上串行化串行化多个信号的串行器; 第二现场可编程门阵列上的解串器，用于反序列化所述多个信号; 以及序列化器和解串器之间的连接。串行器和解串器以大于第一时钟频率的第二时钟频率操作，并且选择第二时钟频率使得多个信号的发送和接收的延迟小于对应于第一时钟频率的周期。

5. 发明申请

US20130262073A1 GENERATING CLOCK SIGNALS FOR A CYCLE ACCURATE, CYCLE REPRODUCIBLE FPGA BASED HARDWARE ACCELERATOR 有权
标题翻译：产生周期精度的周期信号，循环可重复使用基于FPGA的硬件加速器
公开(公告)号：US20130262073A1
公开(公告)日：2013-10-03
申请号：US13435614
申请日：2012-03-30
申请人： Sameth W. Asaad , Mohit Kapur
发明人： Sameth W. Asaad , Mohit Kapur
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F9/455
摘要： A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于为用于模拟被测器件（DUT）的操作的循环精确的基于FPGA的硬件加速器生成时钟信号。在一个实施例中，DUT包括多个器件时钟，以多个频率和定义的频率比产生多个器件时钟信号; 并且FPG硬件加速器包括多个加速器时钟，产生多个加速器时钟信号以操作FPGA硬件加速器来模拟DUT的操作。在一个实施例中，DUT的操作被映射到FPGA硬件加速器，并且加速器时钟信号以多个频率和定义的多个器件时钟频率的频率比生成，以保持DUT和DUT之间的周期精度 FPGA硬件加速器。在一个实施例中，可以使用FPGA硬件加速器来控制多个设备时钟的频率。

6. 发明申请

US20060156215A1 Error type identification circuit for identifying different types of errors in communications devices 失效
标题翻译：用于识别通信设备中不同类型错误的错误类型识别电路
公开(公告)号：US20060156215A1
公开(公告)日：2006-07-13
申请号：US11033077
申请日：2005-01-11
申请人： Mohit Kapur , Jose Tierno
发明人： Mohit Kapur , Jose Tierno
IPC分类号： G06K5/00 , H03M13/00
CPC分类号： G06F11/26
摘要： An apparatus, method, and computer program product are disclosed for identifying types of errors that occur in a communications device under test and where only the presence of an error is indicated by an error checker. Each presence of an error bit in an error signal during a first period of time output from the error data checker is identified. The error bit indicates only that a mismatch occurred between an input signal input into the device and an output signal output from the device. The error bit is generated in response to an error in the device under test. The error bit includes no information about a type of the error. The type of the error is determined by determining a number of occurrences of the error bit in the error signal during the first period of time.
摘要翻译：公开了一种装置，方法和计算机程序产品，用于识别在被测通信设备中出现的错误类型，并且仅错误检查器指示错误的存在。识别在从错误数据检查器输出的第一时间周期内存在错误信号中的错误位的每一个。误差位仅指示输入到器件的输入信号与从器件输出的输出信号之间发生不匹配。响应于被测设备中的错误而产生错误位。错误位不包含有关错误类型的信息。误差的类型通过确定在第一时间段期间误差信号中出现的错误位数来确定。

7. 发明授权

US09286423B2 Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator 有权
标题翻译：为基于FPGA的硬件加速器循环准确和循环重现的存储器
公开(公告)号：US09286423B2
公开(公告)日：2016-03-15
申请号：US13435707
申请日：2012-03-30
申请人： Sameh W. Asaad , Mohit Kapur
发明人： Sameh W. Asaad , Mohit Kapur
IPC分类号： G06F17/50
CPC分类号： G01R31/31703 , G01R31/2851 , G01R31/31727 , G01R31/3177 , G06F17/5027
摘要： A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.
摘要翻译：公开了一种使用现场可编程门阵列（FPGA）来模拟待测器件（DUT）的操作的方法，系统和计算机程序产品。 DUT包括具有多个输入端口的设备存储器，并且FPGA与具有第二数量的输入端口的目标存储器相关联，第二数量小于第一数量。在一个实施例中，给定的一组输入以频率Fd和定义的时间周期被施加到设备存储器，并且给定的一组输入以频率Ft被施加到目标存储器。 Ft大于Fd，并且在设备存储器和目标存储器之间保持循环精度。在一个实施例中，通过将DUT存储器接口协议与目标存储器存储阵列分离来创建DUT存储器的周期精确模型。

8. 发明授权

US08737233B2 Increasing throughput of multiplexed electrical bus in pipe-lined architecture 有权
标题翻译：在管道结构中提高复用电气总线的吞吐量
公开(公告)号：US08737233B2
公开(公告)日：2014-05-27
申请号：US13236109
申请日：2011-09-19
申请人： Sameh Asaad , Bernard V. Brezzo , Mohit Kapur
发明人： Sameh Asaad , Bernard V. Brezzo , Mohit Kapur
IPC分类号： H04L12/26 , H04L12/28 , H04L12/16 , H04L12/66
CPC分类号： H04L12/2602 , G06F13/4059 , H04L12/28 , H04L12/66 , H04L43/00
摘要： Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.
摘要翻译：公开了通过利用计算机或其他系统的可用流水线级来增加多路复用电母线的吞吐量的技术。例如，用于增加连接系统中的至少两个设备的电气总线的吞吐量的方法包括在两个设备中的一个信号接收中引入至少一个信号保持级，使得两个操作设备不受信号从两个设备中的信号传输一个传播到两个设备中的信号接收设备之一所需的电气总线的工作频率的周期数量的限制。优选地，引入到两个装置中的信号接收装置之一中的信号保持级是从两个装置中的信号发送装置之一重新分配的流水线级。

9. 发明申请

US20130262072A1 CYCLE ACCURATE AND CYCLE REPRODUCIBLE MEMORY FOR AN FPGA BASED HARDWARE ACCELERATOR 有权
标题翻译：基于FPGA的硬件加速器的周期精度和周期可重复存储
公开(公告)号：US20130262072A1
公开(公告)日：2013-10-03
申请号：US13435707
申请日：2012-03-30
申请人： Sameth W. Asaad , Mohit Kapur
发明人： Sameth W. Asaad , Mohit Kapur
IPC分类号： G06F17/50
CPC分类号： G01R31/31703 , G01R31/2851 , G01R31/31727 , G01R31/3177 , G06F17/5027
摘要： A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.
摘要翻译：公开了一种使用现场可编程门阵列（FPGA）来模拟待测器件（DUT）的操作的方法，系统和计算机程序产品。 DUT包括具有多个输入端口的设备存储器，并且FPGA与具有第二数量的输入端口的目标存储器相关联，第二数量小于第一数量。在一个实施例中，给定的一组输入以频率Fd和定义的时间周期被施加到设备存储器，并且给定的一组输入以频率Ft被施加到目标存储器。 Ft大于Fd，并且在设备存储器和目标存储器之间保持循环精度。在一个实施例中，通过将DUT存储器接口协议与目标存储器存储阵列分离来创建DUT存储器的周期精确模型。

10. 发明申请

US20130070606A1 INCREASING THROUGHPUT OF MULTIPLEXED ELECTRICAL BUS IN PIPE-LINED ARCHITECTURE 有权
标题翻译：管道式建筑中多路电气总线的增加
公开(公告)号：US20130070606A1
公开(公告)日：2013-03-21
申请号：US13236109
申请日：2011-09-19
申请人： Sameh Asaad , Bernard V. Brezzo , Mohit Kapur
发明人： Sameh Asaad , Bernard V. Brezzo , Mohit Kapur
IPC分类号： H04L12/66 , H04L12/26
CPC分类号： H04L12/2602 , G06F13/4059 , H04L12/28 , H04L12/66 , H04L43/00
摘要： Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.
摘要翻译：公开了通过利用计算机或其他系统的可用流水线级来增加多路复用电母线的吞吐量的技术。例如，用于增加连接系统中的至少两个设备的电气总线的吞吐量的方法包括在两个设备中的一个信号接收中引入至少一个信号保持级，使得两个操作设备不受信号从两个设备中的信号传输一个传播到两个设备中的信号接收设备之一所需的电气总线的工作频率的周期数量的限制。优选地，引入到两个装置中的信号接收装置之一中的信号保持级是从两个装置中的信号发送装置之一重新分配的流水线级。

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