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1. 发明授权

US08241939B2 Semiconductor nanowire sensor device and method for manufacturing the same 有权
标题翻译：半导体纳米线传感器装置及其制造方法
公开(公告)号：US08241939B2
公开(公告)日：2012-08-14
申请号：US12682571
申请日：2008-07-24
申请人： Chan Woo Park , Chang Geun Ahn , Jong Heon Yang , In Bok Baek , Chil Seong Ah , Han Young Yu , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Myung Sim Jun
发明人： Chan Woo Park , Chang Geun Ahn , Jong Heon Yang , In Bok Baek , Chil Seong Ah , Han Young Yu , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Myung Sim Jun
IPC分类号： H01L21/00 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y15/00 , H01L29/0673 , H01L29/78696
摘要： A method for manufacturing a biosensor includes forming a silicon nanowire channel, etching a first conductivity-type single crystalline silicon layer which is a top layer of a Silicon-On-Insulator (SOI) substrate to form a first conductivity-type single crystalline silicon line pattern, doping both sidewalls of the first conductivity-type single crystalline silicon line pattern with impurities of a second conductivity-type opposite to the first conductivity-type to form a second conductivity-type channel, forming second conductivity-type pads for forming electrodes at both ends of the first conductivity-type single crystalline silicon line pattern, forming, in an undoped region of the first conductivity-type single crystalline silicon line pattern, a first electrode for applying a reverse-bias voltage to insulate the first conductivity-type single crystalline silicon line pattern and the second conductivity-type channel from each other, and forming second electrodes for applying a bias voltage across the second conductivity-type channel on the second conductivity-type pad.
摘要翻译：制造生物传感器的方法包括形成硅纳米线通道，蚀刻作为绝缘体上硅（SOI）衬底的顶层的第一导电型单晶硅层，以形成第一导电型单晶硅线以与第一导电类型相反的第二导电类型的杂质掺杂第一导电型单晶硅线图案的两个侧壁以形成第二导电型沟道，形成第二导电型垫，用于在第一导电型单晶硅线图案的两端，在第一导电型单晶硅线图案的未掺杂区域中形成用于施加反向偏置电压以使第一导电型单晶硅线型图案绝缘的第一电极晶体硅线图案和第二导电型沟道，并且形成用于施加双面的第二电极在第二导电型垫上的第二导电类型沟道上的电压。

2. 发明申请

US20100270530A1 SEMICONDUCTOR NANOWIRE SENSOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体纳米传感器器件及其制造方法
公开(公告)号：US20100270530A1
公开(公告)日：2010-10-28
申请号：US12682571
申请日：2008-07-24
申请人： Chan Woo Park , Chang Geun Ahn , Jong Heon Yang , In Book Baek , Chil Seong Ah , Han Young Yu , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Myung Sim Jun
发明人： Chan Woo Park , Chang Geun Ahn , Jong Heon Yang , In Book Baek , Chil Seong Ah , Han Young Yu , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Myung Sim Jun
IPC分类号： H01L29/775 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y15/00 , H01L29/0673 , H01L29/78696
摘要： A method for manufacturing a biosensor device is provided. The method involves forming a silicon nanowire channel with a line width of several nanometers to several tens of nanometers using a typical photolithography process, and using the channel to manufacture a semiconductor nanowire sensor device. The method includes etching a first conductivity-type single crystalline silicon layer which is a top layer of a Silicon-On-Insulator (SOI) substrate to form a first conductivity-type single crystalline silicon line pattern, doping both sidewalls of the first conductivity-type single crystalline silicon line pattern with impurities of a second conductivity-type opposite to the first conductivity-type to form a second conductivity-type channel, forming second conductivity-type pads for forming electrodes at both ends of the first conductivity-type single crystalline silicon line pattern, forming, in an undoped region of the first conductivity-type single crystalline silicon line pattern, a first electrode for applying a reverse-bias voltage to insulate the first conductivity-type single crystalline silicon line pattern and the second conductivity-type channel from each other, and forming second electrodes for applying a bias voltage across the second conductivity-type channel on the second conductivity-type pad.
摘要翻译：提供一种制造生物传感器装置的方法。该方法包括使用典型的光刻工艺形成线宽为几纳米至几十纳米的硅纳米线通道，并使用该通道制造半导体纳米线传感器装置。该方法包括蚀刻作为绝缘体上硅（SOI）衬底的顶层的第一导电型单晶硅层，以形成第一导电型单晶硅线图案，掺杂第一导电型单晶硅线阵列的两个侧壁，形成具有与第一导电类型相反的第二导电类型的杂质的单晶硅线图案，以形成第二导电型沟道，形成用于在第一导电型单晶的两端形成电极的第二导电型焊盘硅线图案，在第一导电型单晶硅线图案的未掺杂区域中形成第一电极，用于施加反向偏置电压以使第一导电型单晶硅线图案和第二导电型并且形成用于在第二导通型通道上施加偏置电压的第二电极导电型垫。

3. 发明授权

US08026508B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08026508B2
公开(公告)日：2011-09-27
申请号：US12498402
申请日：2009-07-07
申请人： Myung-Sim Jun , Moon-Gyu Jang , Tae-Gon Noh , Tae-Moon Roh
发明人： Myung-Sim Jun , Moon-Gyu Jang , Tae-Gon Noh , Tae-Moon Roh
IPC分类号： H01L33/00 , H01L29/78
CPC分类号： H01L29/122 , B82Y10/00 , H01L31/113 , Y10S977/937 , Y10S977/953
摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括：包括第一量子点的单个电子盒，第一量子点上的电荷存储栅极和电荷存储栅极上的第一栅电极，电荷存储栅极与第一量子点交换电荷，第一量子点栅电极调整第一量子点的电位; 以及包括第一量子点下方的第二量子点的单电子晶体管，位于第二量子点下方的源极，漏极和第二栅电极，第二量子点电容耦合到第一量子点，源极与第一量子点接触所述第二量子点的所述漏极与所述一侧面对的另一侧接触，所述第二栅电极调整所述第二量子点的电位。

4. 发明授权

US07893466B2 Semiconductor FET sensor and method of fabricating the same 有权
标题翻译：半导体FET传感器及其制造方法
公开(公告)号：US07893466B2
公开(公告)日：2011-02-22
申请号：US12195302
申请日：2008-08-20
申请人： Jong Heon Yang , In Bok Baek , Chang Geun Ahn , Chan Woo Park , An Soon Kim , Han Young Yu , Chil Seong Ah , Tae Youb Kim , Myung Sim Jun , Moon Gyu Jang
发明人： Jong Heon Yang , In Bok Baek , Chang Geun Ahn , Chan Woo Park , An Soon Kim , Han Young Yu , Chil Seong Ah , Tae Youb Kim , Myung Sim Jun , Moon Gyu Jang
IPC分类号： G01N27/403
CPC分类号： G01N27/4145 , H01L29/66818 , H01L29/7853
摘要： Provided are a semiconductor Field-Effect Transistor (FET) sensor and a method of fabricating the same. The method includes providing a semiconductor substrate, forming a sensor structure having a fin-shaped structure on the semiconductor substrate, injecting ions for electrical ohmic contact into the sensor structure, and depositing a metal electrode on the sensor structure, immobilizing a sensing material to be specifically combined with a target material onto both sidewall surfaces of the fin-shaped structure, and forming a passage on the sensor structure such that the target material passes through the fin-shaped structure.
摘要翻译：提供了一种半导体场效应晶体管（FET）传感器及其制造方法。该方法包括提供半导体衬底，在半导体衬底上形成具有鳍状结构的传感器结构，将用于电欧姆接触的离子注入到传感器结构中，以及在传感器结构上沉积金属电极，将感测材料固定为特别地将目标材料组合到鳍状结构的两个侧壁表面上，并且在传感器结构上形成通道，使得目标材料通过鳍状结构。

5. 发明申请

US20100155703A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100155703A1
公开(公告)日：2010-06-24
申请号：US12498402
申请日：2009-07-07
申请人： Myung-Sim JUN , Moon-Gyu JANG , Tae-Gon NOH , Tae-Moon ROH
发明人： Myung-Sim JUN , Moon-Gyu JANG , Tae-Gon NOH , Tae-Moon ROH
IPC分类号： H01L29/15 , H01L21/336
CPC分类号： H01L29/122 , B82Y10/00 , H01L31/113 , Y10S977/937 , Y10S977/953
摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a single electron box including a first quantum dot, a charge storage gate on the first quantum dot, and a first gate electrode on the charge storage gate, the charge storage gate exchanging charges with the first quantum dot, the first gate electrode adjusting electric potential of the first quantum dot; and a single electron transistor including a second quantum dot below the first quantum dot, a source, a drain, and a second gate electrode below the second quantum dot, the second quantum dot being capacitively coupled to the first quantum dot, the source contacting one side of the second quantum dot, the drain contacting the other side facing the one side, the second gate electrode adjusting electric potential of the second quantum dot.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括：包括第一量子点的单个电子盒，第一量子点上的电荷存储栅极和电荷存储栅极上的第一栅电极，电荷存储栅极与第一量子点交换电荷，第一量子点栅电极调整第一量子点的电位; 以及包括第一量子点下方的第二量子点的单电子晶体管，位于第二量子点下方的源极，漏极和第二栅电极，第二量子点电容耦合到第一量子点，源极与第一量子点接触所述第二量子点的所述漏极与所述一侧面对的另一侧接触，所述第二栅电极调整所述第二量子点的电位。

6. 发明申请

US20090215232A1 SCHOTTKY BARRIER TUNNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：肖特基BARRIER隧道晶体管及其制造方法
公开(公告)号：US20090215232A1
公开(公告)日：2009-08-27
申请号：US12434779
申请日：2009-05-04
申请人： Yark Yeon KIM , Seong Jae LEE , Moon Gyu JANG , Chel Jong CHOI , Myung Sim JUN , Byoung Chul PARK
发明人： Yark Yeon KIM , Seong Jae LEE , Moon Gyu JANG , Chel Jong CHOI , Myung Sim JUN , Byoung Chul PARK
IPC分类号： H01L21/338
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

7. 发明申请

US20090152598A1 BIOSENSOR USING SILICON NANOWIRE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：使用硅纳米管的生物传感器及其制造方法
公开(公告)号：US20090152598A1
公开(公告)日：2009-06-18
申请号：US12240114
申请日：2008-09-29
申请人： In Bok BAEK , Jong Heon Yang , Chang Geun Ahn , Han Young Yu , Chil Seong Ah , Chan Woo Park , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Myung Sim Jun
发明人： In Bok BAEK , Jong Heon Yang , Chang Geun Ahn , Han Young Yu , Chil Seong Ah , Chan Woo Park , An Soon Kim , Tae Youb Kim , Moon Gyu Jang , Myung Sim Jun
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： G01N27/4145 , G01N27/4146
摘要： Provided are a biosensor using a silicon nanowire and a method of manufacturing the same. The silicon nanowire can be formed to have a shape, in which identical patterns are continuously repeated, to enlarge an area in which probe molecules are fixed to the silicon nanowire, thereby increasing detection sensitivity. In addition, the detection sensitivity can be easily adjusted by adjusting a gap between the identical patterns of the silicon nanowire depending on characteristics of target molecules, without adjusting a line width of the silicon nanowire in the conventional art. Further, the gap between the identical patterns of the silicon nanowire can be adjusted depending on characteristics of the target molecule to differentiate detection sensitivities, thereby simultaneously detecting various detection sensitivities.
摘要翻译：提供了使用硅纳米线的生物传感器及其制造方法。可以将硅纳米线形成为具有连续重复相同图案的形状，以扩大探针分子固定在硅纳米线上的面积，从而提高检测灵敏度。此外，通过根据目标分子的特性调整硅纳米线的相同图案之间的间隙，而不调整现有技术中的硅纳米线的线宽，可以容易地调整检测灵敏度。此外，可以根据目标分子的特性来调整硅纳米线的相同图案之间的间隙，以区分检测灵敏度，从而同时检测各种检测灵敏度。

8. 发明授权

US07545000B2 Schottky barrier tunnel transistor and method of manufacturing the same 有权
标题翻译：肖特基势垒隧道晶体管及其制造方法
公开(公告)号：US07545000B2
公开(公告)日：2009-06-09
申请号：US11485837
申请日：2006-07-13
申请人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
发明人： Yark Yeon Kim , Seong Jae Lee , Moon Gyu Jang , Chel Jong Choi , Myung Sim Jun , Byoung Chul Park
IPC分类号： H01L27/01
CPC分类号： H01L29/47 , H01L29/458 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/7839
摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.
摘要翻译：提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道，将肖特基势垒隧道晶体管的栅极侧壁损坏所造成的漏电流减到最小屏障。该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

9. 发明申请

US20080299736A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080299736A1
公开(公告)日：2008-12-04
申请号：US12045797
申请日：2008-03-11
申请人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
发明人： Chel Jong Choi , Moon Gyu Jang , Yark Yeon Kim , Myung Sim Jun , Tae Youb Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28229 , H01L21/28079 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.
摘要翻译：提供一种制造包括使用界面反应形成的高k电介质薄层的半导体器件的方法。该方法包括以下步骤：在硅衬底上形成氧化物层; 使用氧化物层和金属层之间的界面反应，在氧化物层上沉积金属层以形成金属硅酸盐层; 通过蚀刻金属硅酸盐层和金属层形成金属栅极; 以及在形成金属栅极之后在硅衬底中形成轻掺杂漏极（LDD）区域和源极和漏极区域。在该方法中，可以通过更简单的工艺以较低的成本制造具有高品质和高性能的半导体器件。

10. 发明申请

US20080132049A1 METHOD FOR FABRICATING SCHOTTKY BARRIER TUNNEL TRANSISTOR 失效
标题翻译：用于制作肖特基栅栏隧道晶体管的方法
公开(公告)号：US20080132049A1
公开(公告)日：2008-06-05
申请号：US11930902
申请日：2007-10-31
申请人： Yark-Yeon KIM , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
发明人： Yark-Yeon KIM , Seong-Jae Lee , Moon-Gyu Jang , Tae-Youb Kim , Chel-Jong Choi , Myung-Sim Jun , Byoung-Chul Park
IPC分类号： H01L21/334
CPC分类号： H01L29/78618 , H01L29/7839
摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.
摘要翻译：提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

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