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1. 发明授权

US06486015B1 Low temperature carbon rich oxy-nitride for improved RIE selectivity 失效
标题翻译：低温富碳氧氮化物，提高RIE选择性
公开(公告)号：US06486015B1
公开(公告)日：2002-11-26
申请号：US09557363
申请日：2000-04-25
申请人： Nirmal Chaudhary , Richard A. Conti
发明人： Nirmal Chaudhary , Richard A. Conti
IPC分类号： H01L218238
CPC分类号： H01L21/02271 , H01L21/02126 , H01L21/02222 , H01L21/31116 , H01L21/76834 , H01L21/76897 , H01L27/10855 , H01L27/10888
摘要： Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with carbonization throughout layer.
摘要翻译：通过使用在整个层上形成碳氧化的氮氧化硅层来改善蚀刻邻近嵌入结构的特征期间的反应离子蚀刻（RIE）选择性。

2. 发明授权

US06365328B1 Semiconductor structure and manufacturing method 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06365328B1
公开(公告)日：2002-04-02
申请号：US09522883
申请日：2000-03-10
申请人： Hua Shen , David Kotecki , Satish Athavale , Jenny Lian , Laertis Economikos , Fen F. Jamin , Gerhard Kunkel , Nirmal Chaudhary
发明人： Hua Shen , David Kotecki , Satish Athavale , Jenny Lian , Laertis Economikos , Fen F. Jamin , Gerhard Kunkel , Nirmal Chaudhary
IPC分类号： G03F700
CPC分类号： H01L21/7687 , H01L21/76885 , H01L27/10852 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the, electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode. The exposed portions of the second dielectric layer are removed while leaving the portions of the second dielectric layer on the exposed portions of the barrier contact. A material is deposited over exposed portions of the first electrode and over remaining portions of the second dielectric layer in an oxidizing environment. A second electrode is formed for the storage element over the material. In forming a capacitor storage element, the portion of the second dielectric layer on the barrier contact prevents oxidation of the barrier contact during the material formation process.
摘要翻译：一种形成电极的方法。该方法包括通过第一电介质层形成导电插塞。插头从第一电介质层的上表面延伸到半导体衬底中的接触区域。光刻地形成电极，光刻中的掩模配准不对准，导致暴露屏障接触的表面部分。第二电介质层沉积在第一电介质层上，在形成的电极的侧面部分和顶部上方以及屏蔽接触的暴露部分之上。在设置在第一电介质层上的第二电介质层的部分上的第二电介质层的设置在电极的下侧的部分上以及在屏障接触的所述暴露部分上暴露第二电介质层的部分的牺牲材料在形成的电极的顶部和上侧部分上的介电层。第二介电层的暴露部分被去除，同时将第二介电层的部分留在屏障接触的暴露部分上。材料在氧化环境中沉积在第一电极的暴露部分和第二电介质层的剩余部分上。在材料上形成用于存储元件的第二电极。在形成电容器存储元件时，屏障接触部分的第二电介质层在材料形成过程中防止了屏障接触的氧化。

3. 发明申请

US20180294284A1 Approach to the manufacturing of monolithic 3-dimensional high-rise integrated-circuits with vertically-stacked double-sided fully-depleted silicon-on-insulator transistors 审中-公开
公开(公告)号：US20180294284A1
公开(公告)日：2018-10-11
申请号：US15731051
申请日：2017-04-11
申请人： Ahmad Tarakji , Nirmal Chaudhary
发明人： Ahmad Tarakji , Nirmal Chaudhary
IPC分类号： H01L27/12 , H01L23/00
摘要： Method to fabricate high-rise three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all the other known methods and prior arts to fabricate or manufacture 3D-ICs in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAs in monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.

4. 发明授权

US08390080B2 Transistor with dopant-bearing metal in source and drain 有权
标题翻译：在源极和漏极中具有掺杂剂的金属的晶体管
公开(公告)号：US08390080B2
公开(公告)日：2013-03-05
申请号：US12245526
申请日：2008-10-03
申请人： Hong-Jyh Li , Nirmal Chaudhary
发明人： Hong-Jyh Li , Nirmal Chaudhary
IPC分类号： H01L21/02
CPC分类号： H01L21/28194 , H01L21/2254 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed.
摘要翻译：一种晶体管及其制造方法。栅极电介质和栅极形成在工件上，并且晶体管的源极和漏极区域是凹陷的。凹槽填充有掺杂剂的金属，并且使用低温退火工艺在工件附近形成与含掺杂剂的金属区域相邻的掺杂区域。形成具有小的有效氧化物厚度和良好控制的结深度的晶体管。

5. 发明授权

US08085518B2 Electronic circuit, electronic circuit arrangement and method for producing an electronic circuit 有权
标题翻译：电子电路，电子电路装置及电子电路的制造方法
公开(公告)号：US08085518B2
公开(公告)日：2011-12-27
申请号：US11436235
申请日：2006-05-18
申请人： Nirmal Chaudhary , Christian Russ , Thomas Schulz
发明人： Nirmal Chaudhary , Christian Russ , Thomas Schulz
IPC分类号： H02H9/00
CPC分类号： H01L27/1211 , H01L27/0266 , H01L29/785 , H03K17/08142 , H03K17/122 , H03K17/302 , H03K17/6871
摘要： An electronic circuit and method for producing the electronic circuit, where the electronic circuit includes a functional circuit including at least one multigate functional field effect transistor and an ESD protection circuit including at least one multigate ESD protection field effect transistor. The multigate protection field effect transistor is a transistor that is partially depleted of electrical charge carriers, and the trigger voltage of the multigate protection field effect transistor is less than the trigger voltage of the multigate functional field effect transistor.
摘要翻译：一种用于制造电子电路的电子电路和方法，其中电子电路包括包括至少一个多功能场效应晶体管的功能电路和包括至少一个多重ESD保护场效应晶体管的ESD保护电路。多栅极保护场效应晶体管是部分耗尽电荷载流子的晶体管，并且多栅极保护场效应晶体管的触发电压小于多功能场效应晶体管的触发电压。

6. 发明授权

US06551874B2 Self-aligned STI process using nitride hard mask 失效
标题翻译：使用氮化物硬掩模的自对准STI工艺
公开(公告)号：US06551874B2
公开(公告)日：2003-04-22
申请号：US09888287
申请日：2001-06-22
申请人： John Pohl , Nirmal Chaudhary , Veit Klee , Tobias Mono , Paul Schroeder
发明人： John Pohl , Nirmal Chaudhary , Veit Klee , Tobias Mono , Paul Schroeder
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L21/76224
摘要： A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches (216) on a semiconductor wafer (200). The memory cell deep trenches (216) are separated from active areas (212) by a region of substrate (212). A nitride hard mask (230) is formed over the semiconductor wafer (200). The wafer (200) is patterned with the nitride hard mask (230), and the wafer (200) is etched to remove the region of substrate (212) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask (230) is used.
摘要翻译：氮化物硬掩模（230）用于隔离DRAM单元的有效区域。浅沟槽隔离（STI）方法包括在半导体晶片（200）上形成包括深沟槽（216）的存储单元。存储单元深沟槽（216）通过衬底（212）的区域与有源区域（212）分离。氮化物硬掩模（230）形成在半导体晶片（200）上。用氮化物硬掩模（230）对晶片（200）进行构图，并且蚀刻晶片（200）以去除深沟槽和有源区域之间的衬底（212）的区域，以提供浅沟槽隔离。使用对氮化物硬掩模（230）选择性的蚀刻化学品。

7. 发明授权

US06184134B2 Dry process for cleaning residues/polymers after metal etch 有权
标题翻译：金属蚀刻后清洁残留物/聚合物的干法
公开(公告)号：US06184134B2
公开(公告)日：2001-02-06
申请号：US09506892
申请日：2000-02-18
申请人： Nirmal Chaudhary , Xian J. Ning , George Stojakovic
发明人： Nirmal Chaudhary , Xian J. Ning , George Stojakovic
IPC分类号： H01L2144
CPC分类号： H01L21/02071 , Y10S438/906
摘要： An all dry, low temperature process, for complete removal of organics and inorganic residues after metal etch of a microelectronic device comprising: rinsing a microelectronic device having a metallization layer after metal etch with a solution of ammonium hydroxide and hydrogen peroxide; subjecting the rinsed metallization layer to a low temperature GaSonics cleaning by exposing photoresist residue surface of the metallization layer to a fluorine containing reactive gas to form volatile compounds in the presence of a radio frequency input followed by photoresist stripping in an oxygen plasma at low temperature; subjecting the low temperature GaSonics treated residue surface to a gaseous SO3 strip at low temperature to remove additional residue; and rinsing the SO3 stripped material with de-ionized water to remove any remaining resist and residue.
摘要翻译：全部干燥的低温过程，用于在微电子器件的金属蚀刻之后完全去除有机物和无机残留物，包括：在用氢氧化铵和过氧化氢溶液进行金属蚀刻之后，冲洗具有金属化层的微电子器件; 通过将金属化层的光致抗蚀剂残留物表面暴露于含氟反应性气体，在漂移的金属化层的存在下，在低频下在氧等离子体中进行光致抗蚀剂剥离，在射频输入的存在下进行低温GaSonics清洗; 将低温GaSonics处理的残余物表面在低温下经受气态SO 3条带以除去附加残余物; 并用去离子水冲洗SO3汽提材料，以除去任何残留的抗蚀剂和残留物。

8. 发明授权

US10559594B2 Approach to the manufacturing of monolithic 3-dimensional high-rise integrated-circuits with vertically-stacked double-sided fully-depleted silicon-on-insulator transistors 有权
公开(公告)号：US10559594B2
公开(公告)日：2020-02-11
申请号：US15731051
申请日：2017-04-11
申请人： Ahmad Tarakji , Nirmal Chaudhary
发明人： Ahmad Tarakji , Nirmal Chaudhary
IPC分类号： H01L27/12 , H01L23/00 , H01L29/786 , H01L27/02 , H01L21/8226 , H01L21/768
摘要： A new architecture to fabricate high-rise fully monolithic three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all known prior arts in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAS in a monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.

9. 发明授权

US07446379B2 Transistor with dopant-bearing metal in source and drain 有权
标题翻译：在源极和漏极中具有掺杂剂的金属的晶体管
公开(公告)号：US07446379B2
公开(公告)日：2008-11-04
申请号：US11055908
申请日：2005-02-11
申请人： Hong-Jyh Li , Nirmal Chaudhary
发明人： Hong-Jyh Li , Nirmal Chaudhary
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28194 , H01L21/2254 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed.
摘要翻译：一种晶体管及其制造方法。栅极电介质和栅极形成在工件上，并且晶体管的源极和漏极区域是凹陷的。凹槽填充有掺杂剂的金属，并且使用低温退火工艺在工件附近形成与含掺杂剂的金属区域相邻的掺杂区域。形成具有小的有效氧化物厚度和良好控制的结深度的晶体管。

10. 发明授权

US07094650B2 Gate electrode for FinFET device 有权
标题翻译： FinFET器件用栅极
公开(公告)号：US07094650B2
公开(公告)日：2006-08-22
申请号：US11039173
申请日：2005-01-20
申请人： Nirmal Chaudhary , Thomas Schulz , Weize Xiong , Craig Huffman
发明人： Nirmal Chaudhary , Thomas Schulz , Weize Xiong , Craig Huffman
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L29/66795 , H01L29/785
摘要： In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.
摘要翻译：在形成半导体器件的方法中，在包括具有锐利掉落的形貌的衬底上形成自平面化导电层。自平坦化导电层的特征在于比底层形貌基本上更平坦的表面。作为自平坦化层的结果，可以在导电层上形成具有更均匀厚度的掩模层。由于掩模层具有更均匀的厚度，所以掩蔽层可以容易地被图案化，而不会对下面的材料造成损害。除了别的以外，这些技术可以用于制造没有在鳍片和源极/漏极区域周围形成的寄生间隔物的FinFET。

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