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    • 2. 发明授权
      US06294925B1 Programmable logic device 有权
    • Programmable logic device
    • 可编程逻辑器件
    • US06294925B1
    • 2001-09-25
    • US09440460
    • 1999-11-15
    • Albert Chan , Ju Shen , Cyrus Y. Tsui , Rafael C. Camarota
    • Albert Chan , Ju Shen , Cyrus Y. Tsui , Rafael C. Camarota
    • H03K19177
    • H03K19/17728 , H03K17/163
    • An improved programmable logic device that generates output signals skewed in time includes a set of I/O cells and first and second logic circuits. Each logic circuit generates a logic output signal on a respective output line coupled to at least one of the I/O cells. A first delay element coupled to the output line of the first logic circuit is programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to a first delay control signal. A second delay element coupled to the output line of the second logic circuit is programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal. Control circuitry generates the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits. This invention may be used to delay output signals which are not time-critical, allowing fast switching of the limited number of time-critical macrocell output signals.
    • 产生在时间上偏斜的输出信号的改进的可编程逻辑器件包括一组I / O单元和第一和第二逻辑电路。 每个逻辑电路在耦合到至少一个I / O单元的相应输出线上产生逻辑输出信号。 耦合到第一逻辑电路的输出线的第一延迟元件可编程地用于响应于第一延迟控制信号而相对于第二逻辑电路的输出信号延迟第一逻辑电路的输出信号。 耦合到第二逻辑电路的输出线的第二延迟元件可编程地可操作地响应于第二延迟控制信号而延迟第二逻辑电路相对于第一逻辑电路的输出信号的输出信号。 控制电路产生第一和第二延迟控制信号，以防止第一和第二逻辑电路的逻辑输出信号的同时切换。 本发明可以用于延迟不是时间关键的输出信号，允许有限数量的时间关键的宏单元输出信号的快速切换。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US5218240A Programmable logic cell and array with bus repeaters 失效
    • Programmable logic cell and array with bus repeaters
    • 具有总线中继器的可编程逻辑单元和阵列
    • US5218240A
    • 1993-06-08
    • US935116
    • 1992-08-25
    • Rafael C. Camarota , Frederick C. Furtek , Walford W. Ho , Edward H. Browder
    • Rafael C. Camarota , Frederick C. Furtek , Walford W. Ho , Edward H. Browder
    • H03K19/177
    • H03K19/17736 , H03K19/17704 , H03K19/17728 , H03K19/17792
    • A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.
    • 一种包括单元和总线网络的可编程逻辑阵列，其中单元被布置在行和列的二维矩阵中，并且由总线网络互连。 细胞还通过细胞与其四个最近邻居之间的直接连接的二维阵列相互连接，一个在其左侧（或向西部），一个在其右侧（或向东部），一个在其上方（或 到北方）和其中一个（或南部）。 每个单元包括八个输入，八个输出，用于将八个输入复用到两个引线上的装置，以及响应于两个引线上的信号而工作以产生施加到八个输出的输出信号的逻辑装置。 总线网络包括用于阵列的每行和列的本地，转向和快速总线以及用于分配给定行或列的所述总线以形成总线段的中继器装置。 总线网络提供将数据传输到阵列的单元，而不使用单元作为单独的电线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5317209A Dynamic three-state bussing capability in a configurable logic array 失效
    • Dynamic three-state bussing capability in a configurable logic array
    • 可配置逻辑阵列中的动态三态总线功能
    • US5317209A
    • 1994-05-31
    • US14464
    • 1993-02-05
    • Tim Garverick , Rafael C. Camarota
    • Tim Garverick , Rafael C. Camarota
    • H03K17/22 , H03K19/003 , H03K19/173 , H03K19/177
    • H03K19/17736 , H03K17/223 , H03K19/00361 , H03K19/1736 , H03K19/17704 , H03K19/17728
    • The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of rows of logic cells and a plurality of columns of logic cells. The array further includes at least one horizontally aligned local bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned local bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array also includes means for configuring the array such that any logic cell A in the array can write to a local bus which can be linked through the array's bussing network so that logic cell A can be read by any other logic cell B; correspondingly, logic cell B can write to a local bus which is linked through the same components such that data written by logic cell B can be read by logic cell A. Whether a logic element is reading from or writing to a local bus in controlled by a logic function created in the array. The configuration capability is due to means for placing the bus drivers in a high impedance state, means for bidirectional bussing capability due to extra passgates in the array repeaters, and means for connecting horizontal busses to vertical busses through the use of a core cell to bus interface.
    • 本发明提供了一种可配置逻辑阵列，其包括以矩阵形式布置的多个可单独配置的逻辑单元，其包括多行逻辑单元和多列逻辑单元。 该阵列还包括至少一个水平对准的本地总线，其运行在相邻的逻辑单元行之间，相邻行中的逻辑单元可连接到其上，以及至少一个垂直对齐的本地总线，其运行在逻辑单元的相邻列之间， 相邻列可连接到其上。 阵列还包括用于配置阵列的装置，使得阵列中的任何逻辑单元A可以写入可以通过阵列的总线网络链接的本地总线，使得逻辑单元A可以被任何其他逻辑单元B读取; 相应地，逻辑单元B可以写入通过相同组件链接的局部总线，使得由逻辑单元B写入的数据可由逻辑单元A读取。逻辑单元是否从本地总线读取或写入到由 在数组中创建的逻辑函数。 配置能力是由于将总线驱动器置于高阻抗状态的手段，由于阵列中继器中额外的通路，双向总线能力的装置，以及通过使用核心单元到总线将水平总线连接到垂直总线的装置 接口。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5144166A Programmable logic cell and array 失效
    • Programmable logic cell and array
    • 可编程逻辑单元和阵列
    • US5144166A
    • 1992-09-01
    • US608415
    • 1990-11-02
    • Rafael C. Camarota , Frederick C. Furtek , Walford W. Ho , Edward H. Browder
    • Rafael C. Camarota , Frederick C. Furtek , Walford W. Ho , Edward H. Browder
    • H03K19/177
    • H03K19/17728 , H03K19/17704
    • A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.
    • 一种包括单元和总线网络的可编程逻辑阵列，其中单元被布置在行和列的二维矩阵中，并且由总线网络互连。 细胞还通过细胞与其四个最近邻居之间的直接连接的二维阵列相互连接，一个在其左侧（或向西部），一个在其右侧（或向东部），一个在其上方（或 到北方）和其中一个（或南部）。 每个单元包括八个输入，八个输出，用于将八个输入复用到两个引线上的装置，以及响应于两个引线上的信号而工作以产生施加到八个输出的输出信号的逻辑装置。 总线网络包括用于阵列的每行和列的本地，转向和快速总线以及用于分配给定行或列的所述总线以形成总线段的中继器装置。 总线网络提供将数据传输到阵列的单元，而不使用单元作为单独的电线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US5805503A Non-disruptive randomly addressable memory system 失效
    • Non-disruptive randomly addressable memory system
    • 无中断随机可寻址内存系统
    • US5805503A
    • 1998-09-08
    • US582516
    • 1996-01-03
    • Rafael C. Camarota
    • Rafael C. Camarota
    • G11C11/41 , G11C11/405 , G11C13/00 , H03K19/177
    • H03K19/17752 , H03K19/17704 , H03K19/17756 , H03K19/1776
    • An apparatus and method for reprogramming a reconfigurable-logic array is provided whereby a portion of the array can be reconfigured without disrupting the operation of the entire array. Avoiding total disruption of array operation typically requires that the configuration control signals, which determine the configuration of the array, remain substantially non-disrupted during a reprogramming operation. In one embodiment, the reprogramming operates by unique decoding in which an electrical path is established only between the particular storage elements being reprogrammed, thereby avoiding disruption of the configuration control signals provided by other storage elements. In other embodiments, buffers and/or read-modify-write techniques are used to minimize disruption of configuration control signals of storage elements not being reprogrammed.
    • 提供了一种用于重新编程可重构逻辑阵列的装置和方法，其中阵列的一部分可以被重新配置而不中断整个阵列的操作。 避免阵列操作的完全中断通常要求在重新编程操作期间确定阵列的配置的配置控制信号基本上不中断。 在一个实施例中，重编程通过唯一解码操作，其中仅在被重新编程的特定存储元件之间建立电路径，从而避免由其他存储元件提供的配置控制信号的中断。 在其他实施例中，使用缓冲器和/或读 - 修改 - 写入技术来最小化不被重新编程的存储元件的配置控制信号的中断。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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