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    • 3. 发明授权
    • Noisy channel emulator for high speed data
    • 噪声通道模拟器用于高速数据
    • US07426666B2
    • 2008-09-16
    • US10848496
    • 2004-05-18
    • Raul Benet BallesterAdriaan J. De Lind Van WijngaardenRalf DohmenBernd DotterweichSwen Wunderlich
    • Raul Benet BallesterAdriaan J. De Lind Van WijngaardenRalf DohmenBernd DotterweichSwen Wunderlich
    • G01R31/28
    • H04L1/241
    • Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.
    • 通过将从一组基本上不相关的位错误发生器输出的G位的第一错误模式随机分配到N位的第二错误模式中,产生用于高速数据系统的位错误模式,其中G和N是整数,G是 小于或等于N.在一个实施例中,G位错误发生器产生每位周期的G位错误模式。 每个位错误发生器以规定的位错误率运行。 分配元素随机重新排列在N位分组内的单个位周期期间产生的G位的顺序和位置。 N位组对应于可以组合错误位的N个连续的数据位。 每个位错误发生器可以由线性反馈移位寄存器或其等效物来实现。 每个线性反馈移位寄存器可以使用不同的原始多项式和不同的长度。 此外,利用来自少于所有移位寄存器级的输出来产生每个错误位。