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1. 发明授权

US08835261B2 Field effect transistor structure and method of forming same 有权
标题翻译：场效应晶体管结构及其形成方法
公开(公告)号：US08835261B2
公开(公告)日：2014-09-16
申请号：US13046902
申请日：2011-03-14
申请人： Edward J. Nowak , Richard Q. Williams
发明人： Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L21/31
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.
摘要翻译：本公开一般涉及金属氧化物半导体场效应晶体管（MOSFET）结构及其形成方法。 MOSFET结构在衬底上包括至少一个半导体本体; 在所述至少一个半导体主体的顶表面上的电介质盖，其中所述至少一个半导体本体的宽度小于所述电介质盖的宽度; 保护地涂覆所述至少一个半导体主体的栅介质层; 以及栅极电介质层上的至少一个导电栅极。

2. 发明授权

US08417503B2 System and method for target-based compact modeling 失效
公开(公告)号：US08417503B2
公开(公告)日：2013-04-09
申请号：US10023235
申请日：2001-12-17
申请人： Kerry Bernstein , Josef S. Watts , Richard Q. Williams
发明人： Kerry Bernstein , Josef S. Watts , Richard Q. Williams
IPC分类号： G06F17/50 , G06F9/455 , G06F11/30 , G06F19/00
CPC分类号： G06F17/5036 , G06F17/5022
摘要： A method and structure for a computer model of a device has a performance parameter. The performance parameter includes a first bounded range and a second bounded range. The first bounded range has performance parameter variations within a single manufacturing process, and the second bounded range has performance parameter variations of different device designs.

3. 发明授权

US08119474B2 High performance capacitors in planar back gates CMOS 有权
标题翻译：平面后门CMOS中的高性能电容器
公开(公告)号：US08119474B2
公开(公告)日：2012-02-21
申请号：US12688243
申请日：2010-01-15
申请人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
发明人： Andres Bryant , Edward J. Nowak , Richard Q. Williams
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层中的第一板和与第一板电对应的绝缘层之上的第二板。隔离结构在第一板和第二板之间。

4. 发明授权

US07572724B2 Doped single crystal silicon silicided eFuse 有权
标题翻译：掺杂单晶硅硅片eFuse
公开(公告)号：US07572724B2
公开(公告)日：2009-08-11
申请号：US12043226
申请日：2008-03-06
申请人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
发明人： Edward J. Nowak , Jed H. Rankin , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/00
CPC分类号： H01L27/10 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.
摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。将单晶硅层图案化成条带。在构图之前或之后，单晶硅层掺杂有一种或多种杂质。至少单晶硅层的上部然后被硅化以形成硅化带。在一个实施例中，整个单晶硅带被硅化以产生硅化物条。在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。上覆的硅化物材料允许熔丝作为未编程状态的导体。然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

5. 发明申请

US20080303139A1 CHIP-IN-SLOT INTERCONNECT FOR 3D CHIP STACKS 失效
标题翻译：用于3D芯片堆叠的插槽插槽互连
公开(公告)号：US20080303139A1
公开(公告)日：2008-12-11
申请号：US11759651
申请日：2007-06-07
申请人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
发明人： Kerry Bernstein , Timothy J. Dalton , Edmund J. Sprogis , Anthony K. Stamper , Richard Q. Williams
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H01L23/585 , H01L23/13 , H01L23/49833 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/72 , H01L24/73 , H01L24/85 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13025 , H01L2224/18 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/484 , H01L2224/49 , H01L2224/73257 , H01L2224/85 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00013 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/3512 , H01L2224/78 , H01L2224/29099 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.
摘要翻译：一种用于三维半导体芯片堆叠的芯片间插槽互连，特别是具有在半导体芯片上形成边缘连接的能力，其中半导体芯片安装在能够配备嵌入式电路的一个或多个芯片载体中。此外，提供了用于在半导体芯片上制造边缘连接的独特方法，用于形成半导体芯片载体，以及用于制造新颖的半导体和组合芯片载体结构。

6. 发明申请

US20080164535A1 CURVED FINFETS 有权
标题翻译：弯曲的熔体
公开(公告)号：US20080164535A1
公开(公告)日：2008-07-10
申请号：US11621228
申请日：2007-01-09
申请人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
发明人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/66795 , H01L29/7843
摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.
摘要翻译：一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的移动，中央部分不能自由移动。在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

7. 发明授权

US07337420B2 Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models 有权
标题翻译：基于布局的调制方法和紧凑模型中氮化物衬垫应力效应的优化
公开(公告)号：US07337420B2
公开(公告)日：2008-02-26
申请号：US11193711
申请日：2005-07-29
申请人： Dureseti Chidambarrao , Donald L. Jordan , Judith H. McCullen , David M. Onsongo , Tina Wagner , Richard Q. Williams
发明人： Dureseti Chidambarrao , Donald L. Jordan , Judith H. McCullen , David M. Onsongo , Tina Wagner , Richard Q. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , H01L29/7843
摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).
摘要翻译：用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。

8. 发明申请

US20080020531A1 SEMICONDUCTOR DEVICES HAVING TORSIONAL STRESSES 失效
标题翻译：具有扭转应力的半导体器件
公开(公告)号：US20080020531A1
公开(公告)日：2008-01-24
申请号：US11458461
申请日：2006-07-19
申请人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
发明人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/7624 , H01L21/823807 , H01L29/66795 , H01L29/7846 , H01L29/7848 , H01L29/785
摘要： A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.
摘要翻译：提供了一种FET结构，其中设置在有源半导体区域的一个角附近或附近的至少一个应激元件将第一方向上的应力施加到FET的沟道区域的一侧，以向该沟道区域的沟道区域施加扭转应力 FET。在特定实施例中，第二应力元件设置在有源半导体区域的相对拐角处或附近，以将第二方向上的应力施加到FET的沟道区域的相对侧，第二方向与第一方向相反方向。以这种方式，第一和第二应激元件协同工作，将扭曲应力施加到FET的沟道区域。

9. 发明授权

US07217604B2 Structure and method for thin box SOI device 有权
标题翻译：薄盒SOI器件的结构和方法
公开(公告)号：US07217604B2
公开(公告)日：2007-05-15
申请号：US10906014
申请日：2005-01-31
申请人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
发明人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78606 , H01L29/78612
摘要： A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.
摘要翻译：一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物，在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻，在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

10. 发明授权

US06921982B2 FET channel having a strained lattice structure along multiple surfaces 有权
标题翻译： FET通道沿着多个表面具有应变格子结构
公开(公告)号：US06921982B2
公开(公告)日：2005-07-26
申请号：US10626760
申请日：2003-07-21
申请人： Rajiv V Joshi , Richard Q Williams
发明人： Rajiv V Joshi , Richard Q Williams
IPC分类号： H01L20060101 , H01L21/336 , H01L21/8244 , H01L21/84 , H01L27/01 , H01L27/11 , H01L27/12 , H01L29/06 , H01L29/786 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和Si x Ge 1-x x，其中78

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