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1. 发明申请

US20160112534A1 HIERARCHICAL CACHING FOR ONLINE MEDIA 审中-公开
标题翻译：在线媒体的分层缓存
公开(公告)号：US20160112534A1
公开(公告)日：2016-04-21
申请号：US14577039
申请日：2014-12-19
申请人： Shahid AKHTAR , Andre BECK , Rob MURRAY , Ivica RIMAC
发明人： Shahid AKHTAR , Andre BECK , Rob MURRAY , Ivica RIMAC
IPC分类号： H04L29/08 , G06F17/30
CPC分类号： H04L67/2852 , G06F12/0811 , G06F12/123 , G06F16/9574 , H04L67/1097 , H04W4/18
摘要： A method include receiving, at a first cache device, a request to send a first asset to a second device; determining whether the first asset is stored at the first cache device; when the determining whether the first asset is stored at the first cache device indicates that first asset is not stored at the first cache device, obtaining, at the first cache device, the first asset, performing a comparison operation based on an average inter-arrival time of the first asset with respect to the first cache device and a characteristic time of the first cache device, the characteristic time of the first cache device being an average period of time assets cached at the first cache device are cached before being evicted from the first cache device, and determining whether or not to cache the obtained first asset at the first cache device based on the comparison; and sending the obtained first asset to the second device.
摘要翻译：一种方法包括在第一高速缓存设备处接收向第二设备发送第一资产的请求; 确定所述第一资产是否存储在所述第一高速缓存设备处; 当确定第一资产是否存储在第一高速缓存装置中时，指示第一资产没有被存储在第一高速缓存装置中，在第一高速缓存装置获得第一资产，基于平均到达间隔执行比较操作相对于第一高速缓存设备的第一资源的时间和第一高速缓存设备的特征时间，第一高速缓存设备的特征时间是在第一高速缓存设备处被高速缓存的资产的平均时段被高速缓存，第一高速缓存设备，并且基于所述比较来确定是否在所述第一高速缓存设备上缓存所获得的第一资源; 并将获得的第一资产发送到第二设备。

2. 发明授权

US5526510A Method and apparatus for implementing a single clock cycle line replacement in a data cache unit 失效
标题翻译：用于在数据高速缓存单元中实现单个时钟周期线替换的方法和装置
公开(公告)号：US5526510A
公开(公告)日：1996-06-11
申请号：US315889
申请日：1994-09-30
申请人： Haitham Akkary , Mandar S. Joshi , Rob Murray , Brent E. Lince , Paul D. Madland , Andrew F. Glew , Glenn J. Hinton
发明人： Haitham Akkary , Mandar S. Joshi , Rob Murray , Brent E. Lince , Paul D. Madland , Andrew F. Glew , Glenn J. Hinton
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0859
摘要： The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back to main memory. Circuitry is provided for transferring a cache line from the fill buffer into the data cache banks while simultaneously transferring a victim cache line from the data cache banks into the write-back buffer. Such allows the overall replace operation to be performed in only a single clock cycle. In a particular implementation, the data cache unit is employed within a microprocessor capable of speculative and out-of-order processing of memory instructions. Moreover, the microprocessor is incorporated within a multiprocessor computer system wherein each microprocessor is capable of snooping the cache lines of data cache units of each other microprocessor. The data cache unit is also a non-blocking cache.
摘要翻译：数据高速缓存单元包括单独的填充缓冲器和单独的回写缓冲器。填充缓冲器存储用于转移到数据高速缓存单元的数据高速缓存组中的一个或多个高速缓存行。回写缓冲器在回写到主存储器之前存储从数据高速缓冲存储器中逐出的单个高速缓存行。提供电路用于将高速缓存行从填充缓冲器传送到数据高速缓存组，同时将受害缓存行从数据高速缓冲存储体传输到回写缓冲器。这样允许整个替换操作仅在单个时钟周期中执行。在特定实现中，在能够对存储器指令进行推测和无序处理的微处理器中采用数据高速缓存单元。此外，微处理器并入多处理器计算机系统中，其中每个微处理器能够窥探每个其他微处理器的数据高速缓存单元的高速缓存行。数据高速缓存单元也是非阻塞缓存。

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