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1. 发明申请

US20120254877A1 TRANSFERRING ARCHITECTED STATE BETWEEN CORES 有权
标题翻译：转移到CORES之间的建筑状态
公开(公告)号：US20120254877A1
公开(公告)日：2012-10-04
申请号：US13078263
申请日：2011-04-01
申请人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G06F9/46
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/46 , G06F9/4856
摘要： A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.
摘要翻译：一种用于通过在专用互连上直接在处理器核之间传输架构状态来转移架构状态绕过系统存储器的方法和装置。传输可以由具有或不具有软件交互的状态传送接口电路来执行。当状态传输接口电路检测到阻止正确执行与架构状态相对应的线程的错误时，线程的架构状态可以从第一处理核心传送到第二处理核心。可以使用程序指令来启动将线程的架构状态传送到一个或多个其他线程，以通过分配多个线程的处理来并行执行线程或执行多个处理器核之间的负载平衡。

2. 发明授权

US08949836B2 Transferring architected state between cores 有权
公开(公告)号：US08949836B2
公开(公告)日：2015-02-03
申请号：US13078263
申请日：2011-04-01
申请人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G06F9/46 , G06F9/30 , G06F9/48
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/46 , G06F9/4856
摘要： A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.

3. 发明申请

US20120254548A1 ALLOCATING CACHE FOR USE AS A DEDICATED LOCAL STORAGE 有权
标题翻译：分配缓存作为专用本地存储使用
公开(公告)号：US20120254548A1
公开(公告)日：2012-10-04
申请号：US13079520
申请日：2011-04-04
申请人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0815 , G06F12/0871
摘要： A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage.
摘要翻译：一种方法和装置动态地分配和释放高速缓存的一部分以用作专用本地存储。高速缓存行可以被动态分配并被释放以包含在专用本地存储器中。包含在专用本地存储中的缓存条目可能不会被驱逐或无效。另外，在专用本地存储器和后备存储器中包括的缓存条目之间不保持一致性。加载指令可以被配置为分配（例如）锁定数据高速缓存的一部分以包括在专用本地存储器中并将数据加载到专用本地存储器中。加载指令可以被配置为从专用本地存储器读取数据并且解除分配（例如，解锁）包括在专用本地存储器中的数据高速缓存的一部分。

4. 发明申请

US20130159669A1 LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM OF VIRTUAL THREADS ACROSS MULTIPLE HARDWARE THREADS 有权
标题翻译：低延迟可变传输网络，用于通过多个硬件线程的虚拟螺纹的精细平行平行
公开(公告)号：US20130159669A1
公开(公告)日：2013-06-20
申请号：US13330831
申请日：2011-12-20
申请人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3891 , G06F9/544 , G06F15/173
摘要： A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.
摘要翻译：一种方法和电路装置利用多核处理器芯片中的多个处理核心的寄存器文件之间的低延迟可变传输网络来支持跨多个硬件线程的虚拟线程的细粒度并行。可变传输网络上的变量的通信可以通过从源处理核心的寄存器文件中的本地寄存器移动到分配给目的地处理核心中的目的地硬件线程的可变寄存器来启动，使得目标硬件线程可以将变量从变量寄存器移动到目标处理核心中的本地寄存器。

5. 发明授权

US09053037B2 Allocating cache for use as a dedicated local storage 有权
公开(公告)号：US09053037B2
公开(公告)日：2015-06-09
申请号：US13079520
申请日：2011-04-04
申请人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0891 , G06F12/0815 , G06F12/0871
摘要： A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage.

6. 发明授权

US09021237B2 Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread 有权
标题翻译：低延迟变量传输网络通信变量写入源处理核心变量寄存器分配给目标线程到目标处理核心变量寄存器分配给源线程
公开(公告)号：US09021237B2
公开(公告)日：2015-04-28
申请号：US13330831
申请日：2011-12-20
申请人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G06F9/38 , G06F15/173
CPC分类号： G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3891 , G06F9/544 , G06F15/173
摘要： A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.
摘要翻译：一种方法和电路装置利用多核处理器芯片中的多个处理核心的寄存器文件之间的低延迟可变传输网络来支持跨多个硬件线程的虚拟线程的细粒度并行。可变传输网络上的变量的通信可以通过从源处理核心的寄存器文件中的本地寄存器移动到分配给目的地处理核心中的目的地硬件线程的可变寄存器来启动，使得目标硬件线程可以将变量从变量寄存器移动到目标处理核心中的本地寄存器。

7. 发明申请

US20130159799A1 MULTI-CORE PROCESSOR WITH INTERNAL VOTING-BASED BUILT IN SELF TEST (BIST) 有权
标题翻译：具有内部投票功能的多核心处理器（BIST）
公开(公告)号：US20130159799A1
公开(公告)日：2013-06-20
申请号：US13330921
申请日：2011-12-20
申请人： Jeffrey D. Brown , Miguel Comparan , Robert A. Shearer , Alfred T. Watson, III
发明人： Jeffrey D. Brown , Miguel Comparan , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/27 , G01R31/318566 , G06F11/2242
摘要： A method and circuit arrangement utilize scan logic disposed on a multi-core processor integrated circuit device or chip to perform internal voting-based built in self test (BIST) of the chip. Test patterns are generated internally on the chip and communicated to the scan chains within multiple processing cores on the chip. Test results output by the scan chains are compared with one another on the chip, and majority voting is used to identify outlier test results that are indicative of a faulty processing core. A bit position in a faulty test result may be used to identify a faulty latch in a scan chain and/or a faulty functional unit in the faulty processing core, and a faulty processing core and/or a faulty functional unit may be automatically disabled in response to the testing.
摘要翻译：一种方法和电路装置利用设置在多核处理器集成电路器件或芯片上的扫描逻辑来执行基于内部投票的内置自检（BIST）芯片。测试模式在芯片内部产生，并传送到芯片上多个处理核心内的扫描链。扫描链输出的测试结果在芯片上相互比较，多数表决用于识别表示故障处理核心的异常值测试结果。故障测试结果中的位位置可用于识别故障处理核心中的扫描链和/或故障功能单元中的故障锁存器，并且故障处理核心和/或故障功能单元可能被自动禁用响应测试。

8. 发明授权

US08856602B2 Multi-core processor with internal voting-based built in self test (BIST) 有权
标题翻译：具有内部投票的多核处理器内置自检（BIST）
公开(公告)号：US08856602B2
公开(公告)日：2014-10-07
申请号：US13330921
申请日：2011-12-20
申请人： Jeffrey D. Brown , Miguel Comparan , Robert A. Shearer , Alfred T. Watson, III
发明人： Jeffrey D. Brown , Miguel Comparan , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G01R31/28
CPC分类号： G06F11/27 , G01R31/318566 , G06F11/2242
摘要： A method and circuit arrangement utilize scan logic disposed on a multi-core processor integrated circuit device or chip to perform internal voting-based built in self test (BIST) of the chip. Test patterns are generated internally on the chip and communicated to the scan chains within multiple processing cores on the chip. Test results output by the scan chains are compared with one another on the chip, and majority voting is used to identify outlier test results that are indicative of a faulty processing core. A bit position in a faulty test result may be used to identify a faulty latch in a scan chain and/or a faulty functional unit in the faulty processing core, and a faulty processing core and/or a faulty functional unit may be automatically disabled in response to the testing.
摘要翻译：一种方法和电路装置利用设置在多核处理器集成电路器件或芯片上的扫描逻辑来执行基于内部投票的内置自检（BIST）芯片。测试模式在芯片内部产生，并传送到芯片上多个处理核心内的扫描链。扫描链输出的测试结果在芯片上相互比较，多数表决用于识别表示故障处理核心的异常值测试结果。故障测试结果中的位位置可用于识别故障处理核心中的扫描链和/或故障功能单元中的故障锁存器，并且故障处理核心和/或故障功能单元可能被自动禁用响应测试。

9. 发明申请

US20120144253A1 HARD MEMORY ARRAY FAILURE RECOVERY UTILIZING LOCKING STRUCTURE 失效
标题翻译：硬记忆阵列故障恢复利用锁定结构
公开(公告)号：US20120144253A1
公开(公告)日：2012-06-07
申请号：US12961947
申请日：2010-12-07
申请人： Miguel Comparan , Mark G. Kupferschmidt , Robert A. Shearer
发明人： Miguel Comparan , Mark G. Kupferschmidt , Robert A. Shearer
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/0727 , G06F11/0724 , G06F11/073 , G06F11/0772
摘要： A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice.
摘要翻译：公开了一种用于管理采用锁定的存储器系统中的硬故障的技术。内存系统中的内存单元维护错误计数。当错误计数表示硬故障时，内存单元被锁定以供进一步使用。分配一组任意错误计数器来记录访问内存单元所产生的错误。本发明的实施例有利地使得即使在一个或多个内部硬盘存储器故障之后，系统也能够继续可靠的操作。其他实施例有利地使得制造商能够回收部分故障的设备，并且将设备部署为具有较低性能规范而不是丢弃设备，否则将由常规实践指出。

10. 发明授权

US08719507B2 Near neighbor data cache sharing 有权
标题翻译：近邻数据缓存共享
公开(公告)号：US08719507B2
公开(公告)日：2014-05-06
申请号：US13343236
申请日：2012-01-04
申请人： Miguel Comparan , Robert A. Shearer
发明人： Miguel Comparan , Robert A. Shearer
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0893 , G06F12/0895 , G06F12/0897
摘要： Parallel computing environments, where threads executing in neighboring processors may access the same set of data, may be designed and configured to share one or more levels of cache memory. Before a processor forwards a request for data to a higher level of cache memory following a cache miss, the processor may determine whether a neighboring processor has the data stored in a local cache memory. If so, the processor may forward the request to the neighboring processor to retrieve the data. Because access to the cache memories for the two processors is shared, the effective size of the memory is increased. This may advantageously decrease cache misses for each level of shared cache memory without increasing the individual size of the caches on the processor chip.
摘要翻译：在相邻处理器中执行的线程可以访问同一组数据的并行计算环境可被设计和配置为共享一个或多个级别的高速缓冲存储器。在处理器在高速缓存未命中之后将数据请求转发到更高级别的高速缓冲存储器之前，处理器可以确定相邻处理器是否具有存储在本地高速缓冲存储器中的数据。如果是这样，则处理器可以将该请求转发到相邻处理器以检索数据。因为对两个处理器的高速缓冲存储器的访问被共享，所以存储器的有效大小增加。这可以有利地减少每个级别的共享高速缓冲存储器的高速缓存未命中，而不增加处理器芯片上的高速缓存的单独大小。

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