专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20220249853A1 Implantable Pulse Generator Having Rectangular Shock Waveform 有权
公开(公告)号：US20220249853A1
公开(公告)日：2022-08-11
申请号：US17630323
申请日：2020-07-21
申请人： BIOTRONIK SE & Co. KG
发明人： Thomas Doerr , Ingo Weiss
IPC分类号： A61N1/39 , H02J7/00 , H03K3/015 , H03K3/57
摘要： The present invention relates an implantable pulse generator comprising an electric circuit, wherein the electric circuit comprises: a primary energy store, at least one secondary energy store, and a control unit, wherein the control unit is configured to activate an electric switch in the electric circuit in such a way that, in a first interval of a first phase of a pulse delivery, the primary energy store is discharged via a therapeutic current path, and to activate an electric switch in the electric circuit in such a way that, in a second interval of the first phase of the pulse delivery, the secondary energy store is discharged via the therapeutic current path, wherein the primary energy store and the at least one secondary energy store are fixedly connected, or connectable, in series, and wherein the implantable pulse generator is designed to deliver a shock having an approximately rectangular pulse waveform.

2. 发明授权

US09401677B2 Split transformer based digitally controlled oscillator and DC-coupled buffer circuit therefor 有权
标题翻译：基于分立变压器的数控振荡器和直流耦合缓冲电路
公开(公告)号：US09401677B2
公开(公告)日：2016-07-26
申请号：US14831119
申请日：2015-08-20
申请人： Augusto Ronchini Ximenes , Robert Bogdan Staszewski
发明人： Augusto Ronchini Ximenes , Robert Bogdan Staszewski
IPC分类号： H03B5/12 , H03B1/00 , H03K3/015 , G04F10/00 , H03L7/08 , H03M1/00 , H03L7/093 , H03M1/20 , H03L7/089 , H03L7/197 , H03K3/03
CPC分类号： H03B5/1265 , G04F10/005 , H03B1/00 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03J2200/10 , H03K3/015 , H03K3/0315 , H03L7/0802 , H03L7/0893 , H03L7/093 , H03L7/1976 , H03L2207/50 , H03M1/002 , H03M1/201
摘要： A novel and useful LC-tank digitally controlled oscillator (DCO) incorporating a split transformer configuration. The LC-tank oscillator exhibits a significant reduction in area such that it is comparable in size to conventional ring oscillators (ROs) while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The oscillator incorporates an ultra-compact split transformer topology that is less susceptible to common-mode electromagnetic interference than regular high-Q LC tanks which is highly desirable in SoC environments. The oscillator, together with a novel dc-coupled buffer, can be incorporated within a wide range of circuit applications, including clock generators and an all-digital phase-locked loop (ADPLL) intended for wireline applications.
摘要翻译：一种新颖有用的LC-tank数字控制振荡器（DCO），其包含分离变压器配置。 LC-tank振荡器显示出显着的面积减小，使得它在尺寸上与常规的环形振荡器（RO）相当，同时仍然保持其显着的相位噪声特征以及对供应变化的低灵敏度。该振荡器包含一个超紧凑型分离式变压器拓扑，它比常规高Q液相色谱箱容易受到共模电磁干扰的影响，这在SoC环境中是非常需要的。该振荡器与一个新颖的直流耦合缓冲器可以并入广泛的电路应用中，包括时钟发生器和用于有线应用的全数字锁相环（ADPLL）。

3. 发明申请

US20160118961A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160118961A1
公开(公告)日：2016-04-28
申请号：US14922340
申请日：2015-10-26
申请人： Rohm Co., Ltd.
发明人： Masashi Nagasato
IPC分类号： H03K3/015 , H02P27/04 , H03K17/687
CPC分类号： H02P27/04 , H01L23/64 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H02M1/34 , H02M3/158 , H02M7/5387 , H02M2001/348 , H03K17/687 , H03K17/6872 , H05K1/0243 , H05K1/025
摘要： A semiconductor device disclosed in the present specification has a structure that includes: a first terminal that is to be externally connected to a power source line; a second terminal that is to be externally connected to a ground line; a third terminal that is internally connected to the first terminal and to be externally connected to a first terminal of a bypass capacitor; and a fourth terminal that is internally connected to the second terminal and to be externally connected to a second terminal of the bypass capacitor.
摘要翻译：本说明书中公开的半导体装置具有：将外部连接到电源线的第一端子，将外部连接到地线的第二端子; 第三端子，其内部连接到第一端子并且外部连接到旁路电容器的第一端子; 以及第四端子，其内部连接到第二端子并且外部连接到旁路电容器的第二端子。

4. 发明授权

US3883756A Pulse generator with automatic timing adjustment for constant duty cycle 失效
标题翻译：脉冲发生器，具有自动定时调整，用于恒定占空比
公开(公告)号：US3883756A
公开(公告)日：1975-05-13
申请号：US42873073
申请日：1973-12-27
申请人： BURROUGHS CORP
发明人： DRAGON THOMAS J
IPC分类号： H03K3/015 , H03K5/156 , H03K5/04
CPC分类号： H03K3/015 , H03K5/1565
摘要： A circuit for generating a waveform comprising a train of rectangular pulses in response to a train of trigger signals such that the duration of each rectangular pulse is a precise multiple of the time lapse between pulses, in spite of variation in the waveform''s absolute period. The circuit employs a flip-flop set by a trigger signal and timed to reset by a ramp signal-toreference voltage comparison circuit. The output of the flip-flop is subject to continuous adjustment by the circuit to achieve the desired waveform, and to this end is monitored by a first discharging current source producing a fixed current and activated by the set state and a second charging current source producing a fixed multiple, the desired time lapse multiple, of the first current and activated by the reset state. Should one of the current sources be kept on too long by a deviation of the relative pulse (set) and lapse (reset) durations from the desired multiple, a capacitor driven by the two sources will be relatively over-or undercharged, depending on which current source is overactivated, and the charge and hence voltage change will be monitored to adjust the reference voltage to return to the desired timing multiple.
摘要翻译：一种用于响应于一串触发信号产生包括一串矩形脉冲的波形的电路，使得每个矩形脉冲的持续时间是脉冲之间的时间间隔的精确倍数，尽管波形的绝对周期的变化。该电路采用由触发信号设置的触发器，并由斜坡信号对参考电压比较电路定时复位。触发器的输出由电路进行连续调节以实现期望的波形，并且由此产生固定电流并由设定状态激活的第一放电电流源来监测触发器的输出，并且产生第二充电电流源固定倍数，第一电流的期望时间延迟倍数，并由复位状态激活。如果通过相对脉冲（设定）和期望倍数的经过（复位）持续时间的偏差，电流源之一应保持太长时间，由两个源驱动的电容器将相对过度或不足，取决于哪个电流源被过激活，并且将监视电荷和因此的电压变化以调整参考电压以返回到期望的定时倍数。

5. 发明授权

US10158353B2 Duty cycle correction method 有权
公开(公告)号：US10158353B2
公开(公告)日：2018-12-18
申请号：US15496294
申请日：2017-04-25
申请人： Cavium, LLC
发明人： David Lin
IPC分类号： H03K3/015 , H03K5/156 , H03L7/081 , H03K5/159 , H03M1/10
摘要： The present disclosure includes circuits and methods that adjust and correct duty cycles of circuits. The circuits and methods receive a signal from a first circuit and forward the received signal to a second circuit that retrieves a first setting (X) that provides a measure of duty cycle of the received signal. The circuits and methods then invert the received signal, retrain the second circuit based upon the inverted received signal, and retrieve a second setting (Y) of the retrained second circuit. The second setting (Y) provides a measure of duty cycle of the inverted received signal. The circuits and methods then adjust the duty cycle of the received signal based upon the first and second settings (X, Y) and further retrain of the second circuit to provide an improved duty cycle in a direction closer to 50 percent.

6. 发明申请

US20180129237A1 BANDGAP REFERENCE CIRCUIT AND METHOD OF USING THE SAME 审中-公开
公开(公告)号：US20180129237A1
公开(公告)日：2018-05-10
申请号：US15802663
申请日：2017-11-03
申请人： Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人： Josh YANG , Zhi Bing DENG , Cheng Tai HUANG , Cheng Yi HUANG , Wen Jun WENG , Jun Tao GUO
IPC分类号： G05F3/24 , H03K3/011 , G05F1/46 , H03K3/015
摘要： A bandgap reference circuit and method of using the same are provided. The bandgap reference circuit includes a startup component; an output component; and a bandgap core component coupled there-between. The bandgap core component includes a reference point having a voltage associated with an output signal of the output component. A controller is configured for controlling the bandgap core component and the output component to switch between a low power consumption mode and a normal operation mode based on the voltage at the reference point. When the bandgap core component and the output component operate in the normal operation mode, the bandgap reference circuit outputs a stable voltage and has a first power consumption. When the bandgap core component and the output component operate in the low power consumption mode, the bandgap reference circuit has a second power consumption less than the first power consumption.

7. 发明申请

US20170317665A1 Square Pulse Optical Transmission Circuit 审中-公开
公开(公告)号：US20170317665A1
公开(公告)日：2017-11-02
申请号：US15363743
申请日：2016-11-29
申请人： STMicroelectronics (Alps) SAS
发明人： Xavier Branca
IPC分类号： H03K3/015 , H02M7/537 , G01S17/10 , H03K3/017 , G01S7/484
CPC分类号： H03K3/015 , G01S7/484 , G01S17/10 , H02M7/537 , H03K3/017 , H03K17/78
摘要： An optical emission circuit includes a power supply source and a regulation circuit coupled to control the power supply source. An optical source and a first switch are coupled in series to the power supply source. A square pulse signal source has an output coupled to a control input of the first switch. The square pulse signal source is configured to provide a square pulse signal. The regulation circuit regulates the current supplied by the power supply source according to a product of a peak current set point by a duty cycle of the square pulse signal.

8. 发明授权

US09054719B2 Current compensation circuit 有权
标题翻译：电流补偿电路
公开(公告)号：US09054719B2
公开(公告)日：2015-06-09
申请号：US14206163
申请日：2014-03-12
申请人： ADVANTEST CORPORATION
发明人： Jun'ichi Matsumoto
IPC分类号： H03M9/00 , H04L7/00 , G01R31/319 , H03K3/015
CPC分类号： H03M9/00 , G01R31/31922 , H03K3/015 , H04J3/047 , H04L7/00
摘要： A first circuit operates in synchronization with a first clock having a first frequency, and generates N parallel data sets for every cycle period of the first clock. An interface circuit time-division multiplexes the N data sets received from the first circuit. A second circuit processes the N data set thus time-division multiplexed, in synchronization with a second clock having a second frequency which is N times the first frequency. A judgment unit judges whether or not the N data sets are effective data which instructs a flip-flop group, configured as a state holding element included in the second circuit, to generate an effective state transition. In a cycle period in which the N data sets are ineffective, a data replacement unit replaces at least a part of the N data sets with current compensation data DCMP.
摘要翻译：第一电路与具有第一频率的第一时钟同步地操作，并且在第一时钟的每个周期周期生成N个并行数据集。接口电路对从第一电路接收的N个数据集进行时分复用。第二电路与具有第二频率的N倍的第二时钟同步地处理N数据集，从而进行时分复用。判断单元判断N个数据组是否是指示被配置为包括在第二电路中的状态保持元件的触发器组的有效数据，以产生有效状态转换。在N个数据组无效的循环周期中，数据替换单元用当前补偿数据DCMP替换N个数据集的至少一部分。

9. 发明申请

US20130241812A1 OUTPUT CONTROL CIRCUIT, SCANNING LINE DRIVING CIRCUIT OF ELECTRO-OPTIC DEVICE, ELECTRO-OPTIC DEVICE AND ELECTRONIC APPARATUS 有权
标题翻译：输出控制电路，电光装置的扫描线驱动电路，电光装置和电子装置
公开(公告)号：US20130241812A1
公开(公告)日：2013-09-19
申请号：US13789297
申请日：2013-03-07
申请人： SEIKO EPSON CORPORATION
发明人： Shinsuke Fujikawa
IPC分类号： G09G5/00 , H03K3/015
CPC分类号： G09G5/003 , G09G3/2022 , G09G3/3677 , G09G2310/0216 , G09G2310/0286 , G09G2310/08 , H03K3/015
摘要： An output control circuit is configured to have a first circuit which includes a NOT circuit, a NAND circuit and a transmission gate as a first sub circuit, and a second circuit which includes a NAND circuit as a second sub circuit. The NAND circuit controls a transmission to the NAND circuit of the enable signal by the transmission gate based on signal which has been logic reversed by the NOT circuit and the NAND circuit.
摘要翻译：输出控制电路被配置为具有包括NOT电路，NAND电路和作为第一子电路的传输门的第一电路，以及包括作为第二子电路的NAND电路的第二电路。 NAND电路基于由NOT电路和NAND电路已被逻辑反相的信号，控制通过传输门对NAND电路的使能信号的传输。

10. 发明申请

US20130229218A1 LATCH CIRCUIT AND SEMICONDUCTOR DEVICE 有权
标题翻译：锁存电路和半导体器件
公开(公告)号：US20130229218A1
公开(公告)日：2013-09-05
申请号：US13782640
申请日：2013-03-01
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Tatsuji Nishijima
IPC分类号： H03K3/015
CPC分类号： H03K3/012 , H03K3/015 , H03K3/356008
摘要： A nonvolatile latch circuit is provided. In the latch circuit, a transistor in which a channel region is formed with an oxide semiconductor, which is a wide band gap semiconductor, is included, and data is stored in a node formed by one terminal of a capacitor and one of a source and a drain of the transistor, and is brought into a floating state when the transistor is turned off. After that, even when charge stored in the node is insufficient at time of restoring the data, charge is supplied by feedback; therefore, time necessary for restoring the data can be shortened and even when the power supply is restarted in the state of storing data, the data can be restored at high speed.
摘要翻译：提供非易失性锁存电路。在锁存电路中，包括其中沟道区域形成有作为宽带隙半导体的氧化物半导体的晶体管，并且数据存储在由电容器的一个端子形成的节点中，并且源极和晶体管的漏极，并且当晶体管截止时，其被置于浮置状态。此后，即使在恢复数据时，存储在节点中的电荷不足，则通过反馈提供电荷; 因此，可以缩短恢复数据所需的时间，即使在存储数据的状态下重新开始电源的情况下，也可以高速地恢复数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式