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1. 发明授权

US09257839B2 Systems and methods for managing multiple power domains 有权
标题翻译：用于管理多个电源域的系统和方法
公开(公告)号：US09257839B2
公开(公告)日：2016-02-09
申请号：US14193921
申请日：2014-02-28
申请人： Khurram Waheed , William S. King
发明人： Khurram Waheed , William S. King
IPC分类号： H02J1/04 , H01L31/00 , H02J1/14
CPC分类号： H02J1/14 , H02J1/08 , H02J7/0063 , H02J9/005 , Y10T307/422
摘要： A system includes a voltage converter configured to provide a first output voltage at a first output terminal, wherein the first output voltage is from a first group comprising a first high regulation voltage, a first low regulation voltage, and a battery voltage. A first plurality of circuits has power supply terminals coupled to the first output terminal. A power control circuit uses information about operational states of the plurality of circuits to direct the voltage converter to provide the first output voltage from the first group appropriate for the operational states of the first plurality of circuits.
摘要翻译：一种系统包括：电压转换器，被配置为在第一输出端提供第一输出电压，其中所述第一输出电压来自包括第一高调节电压，第一低调节电压和电池电压的第一组。第一组多个电路具有耦合到第一输出端子的电源端子。功率控制电路使用关于多个电路的操作状态的信息来引导电压转换器提供适于第一多个电路的操作状态的来自第一组的第一输出电压。

2. 发明申请

US20150222297A1 VITERBI DECODING DEVICE AND METHOD FOR DECODING A SIGNAL PRODUCED BY A CONVOLUTIONAL ENCODER 有权
标题翻译： VITERBI解码设备和用于解码由转换编码器产生的信号的方法
公开(公告)号：US20150222297A1
公开(公告)日：2015-08-06
申请号：US14427029
申请日：2012-09-14
申请人： Mihai-Ionut Stanciu , Ioan-Virgil Dragomir , Khurram Waheed
发明人： Mihai-Ionut Stanciu , Ioan-Virgil Dragomir , Khurram Waheed
IPC分类号： H03M13/41 , H04L1/00
CPC分类号： H03M13/41 , H03M13/4107 , H04L1/0054
摘要： A convolutional encoder may have N different states, each having two predecessor states, each branch from each of the two predecessor states having a static code word CW=(B0, B1) and produces a signal having a sequence of the code words. A Viterbi decoding device includes an analog-to-digital conversion unit arranged to extract a soft symbol S=(S1, S2) from the signal; and a digital processing unit connected to the analog-to-digital conversion unit and arranged to compute, for each of the N states, a branch metric value BM_0_K in dependence on the soft symbol S, K being an index identifying the respective state. The digital processing unit may store the soft symbol S as a complex number; and compute a complex branch metric value BM_0_(K, K′)=BM_0_K+J*BM_0_K′ in a complex number format on the basis of the soft symbol S, with K different from K′.
摘要翻译：卷积编码器可以具有N个不同的状态，每个具有两个前导状态，每个前两个状态中的每一个的分支具有静态码字CW =（B0，B1），并且产生具有码字序列的信号。维特比解码装置包括：模拟 - 数字转换单元，被配置为从信号中提取软符号S =（S1，S2）; 以及数字处理单元，连接到所述模数转换单元，并且被布置为根据所述软符号S计算所述N个状态中的每一个的分支度量值BM_0_K，K是识别相应状态的索引。数字处理单元可以将软符号S存储为复数; 并且基于软符号S计算复数分支度量值BM_0_（K，K'）= BM_0_K + J * BM_0_K'，其中K与K'不同。

3. 发明授权

US08126401B2 Transmitter PLL with bandwidth on demand 有权
标题翻译：发射器PLL，带宽需求
公开(公告)号：US08126401B2
公开(公告)日：2012-02-28
申请号：US12412790
申请日：2009-03-27
申请人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
发明人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
IPC分类号： H04B1/00
CPC分类号： H03L7/085 , H03L7/093 , H03L7/0991 , H03L2207/50 , H04L27/361
摘要： An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.
摘要翻译：本发明的一个实施例提供具有锁相环的发射机，其具有动态可控的环路带宽。发射调制器耦合到PLL以响应于发射符号执行矢量调制。每个发送符号包括振幅信号和相位信号。控制器耦合到PLL和发射调制器，并且可操作以检测发射符号的标准何时跨越阈值并响应于跨越阈值来调整环路带宽。传输符号的标准可以是振幅信号或相位信号的函数的函数，并且可以是振幅信号，振幅信号的一阶导数，振幅信号的二阶导数，幅度的平方信号，幅度信号平方的导数，相位信号或相位信号的导数。

4. 发明授权

US08045670B2 Interpolative all-digital phase locked loop 有权
标题翻译：内插全数字锁相环
公开(公告)号：US08045670B2
公开(公告)日：2011-10-25
申请号：US12022931
申请日：2008-01-30
申请人： Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
发明人： Khurram Waheed , Robert Bogdan Staszewski , John L. Wallberg , Sudheer K. Vemulapalli
IPC分类号： H03D3/24
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. An interpolator is coupled to the phase detection circuit for performing a sample rate conversion between the reference clock and the clock derived from the RF clock signal.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。内插器耦合到相位检测电路，用于执行参考时钟和从RF时钟信号导出的时钟之间的采样率转换。

5. 发明申请

US20080317188A1 Digital Phase Locked Loop with Integer Channel Mitigation 有权
标题翻译：具有整数通道缓解的数字锁相环
公开(公告)号：US20080317188A1
公开(公告)日：2008-12-25
申请号：US12024881
申请日：2008-02-01
申请人： Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
发明人： Robert Bogdan Staszewski , Sudheer K. Vemulapalli , John L. Wallberg , Khurram Waheed
IPC分类号： H04L7/00
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生具有多个相位的RF时钟信号。耦合开关以接收RF时钟，并且可操作以选择多个相位中的一个。相位检测电路耦合到开关并且可操作以接收所选择的相位并且提供指示参考时钟和所选相位之间的时间差的数字相位误差样本。

6. 发明申请

US20080315960A1 Digital Phase Locked Loop with Gear Shifting 有权
标题翻译：数字锁相环与齿轮换档
公开(公告)号：US20080315960A1
公开(公告)日：2008-12-25
申请号：US12137332
申请日：2008-06-11
申请人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
发明人： Khurram Waheed , John Wallberg , Robert Bogdan Staszewski , Sudheer Vemulapalli
IPC分类号： H03L7/099 , H03B5/12
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha-α) and an integral loop gain control having a programmable loop gain coefficient (rho-ρ). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。连接可编程滤波器以接收相位误差样本并连接以提供具有对可控振荡器的增益和相位裕度的滤波输出。可编程滤波器包括具有可编程环路增益系数（α-α）的比例环路增益控制和具有可编程环路增益系数（rho-rho））的积分环路增益控制。 Alpha和rho被配置为同时编程地改变，并且被选择为使得增益改变并且相位裕度保持基本上不变

7. 发明申请

US20080309524A1 Second-Order Polynomial, Interpolation-Based, Sampling Rate Converter and Method and Transmitters Employing the Same 审中-公开
标题翻译：二阶多项式，基于插值的采样率转换器及其使用的方法和发送器
公开(公告)号：US20080309524A1
公开(公告)日：2008-12-18
申请号：US12121090
申请日：2008-05-15
申请人： Ioannis L. Syllaios , Khurram Waheed , Robert B. Staszewski
发明人： Ioannis L. Syllaios , Khurram Waheed , Robert B. Staszewski
IPC分类号： H03M7/00
CPC分类号： H03H17/0685 , H03H17/028
摘要： A sampling rate converter, a method of performing digital sampling rate conversion and a wireless transmitter incorporating the filter or the method. In one embodiment, the sampling rate converter includes: (1) an input configured to receive digital data from a first clock domain sampled at a first sampling rate, (2) an output configured to provide digital data to a second clock domain sampled at a second sampling rate that differs from the first sampling rate and (3) a filter with a second-order, polynomial-based impulse response coupled to the input and the output and configured to apply coefficients having only one nonunitary divisor to the digital data from the first clock domain.
摘要翻译：采样率转换器，执行数字采样率转换的方法和包含滤波器或方法的无线发射器。在一个实施例中，采样率转换器包括：（1）被配置为从以第一采样率采样的第一时钟域接收数字数据的输入，（2）被配置为将数字数据提供给在第二采样率与第一采样率不同，以及（3）具有耦合到输入和输出的二阶多项式的脉冲响应的滤波器，并且被配置为将仅具有一个非维数除数的系数应用于来自第一个时钟域

8. 发明申请

US20070189417A1 PRECISE DELAY ALIGNMENT BETWEEN AMPLITUDE AND PHASE/FREQUENCY MODULATION PATHS IN A DIGITAL POLAR TRANSMITTER 有权
标题翻译：数字极性放大器中的幅度和相位/频率调制方式之间的精确延迟对准
公开(公告)号：US20070189417A1
公开(公告)日：2007-08-16
申请号：US11675565
申请日：2007-02-15
申请人： Khurram Waheed , Jayawardan Janardhanan , Sameh S. Rezeq , Robert B. Staszewski , Saket Jalan
发明人： Khurram Waheed , Jayawardan Janardhanan , Sameh S. Rezeq , Robert B. Staszewski , Saket Jalan
IPC分类号： H04L27/04 , H04L7/00
CPC分类号： H04L27/368 , H03C5/00 , H04L7/0029 , H04L7/0041 , H04L7/005 , H04L7/0079 , H04L7/02
摘要： A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.
摘要翻译：数字极性发射机的幅度和相位/频率调制路径之间的延迟对准的新型装置和方法。本发明提供了一种全数字延迟对准机制，其通过考虑发射机的数字电路模块中的处理延迟以及通过使用分布在几个时钟域上的可编程延迟元件来实现比纳秒对准更好的方法。分接延迟线补偿模拟元件（如DCO，分频器，四通道开关，缓冲器，电平移位器和数字预功率放大器（DPA））中的传播和稳定延迟。提供了一种信号相关机制，其中来自要匹配的幅度和相位/频率调制路径的数据首先被内插，然后进行交叉相关，以获得比时钟域更好的比较。在发射机的ADPLL部分内，使用多个时钟域，抽头延迟线和时钟调整电路来证明ADPLL中的参考点和直接点注入点的精确对准。

9. 发明申请

US20070188244A1 Harmonic Characterization and Correction of Device Mismatch 有权
标题翻译：谐波特征和装置不匹配的校正
公开(公告)号：US20070188244A1
公开(公告)日：2007-08-16
申请号：US11618605
申请日：2006-12-29
申请人： Khurram Waheed , Robert B. Staszewski
发明人： Khurram Waheed , Robert B. Staszewski
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L7/10 , H03L2207/50
摘要： A novel apparatus for and method of harmonic characterization and ratio correction of device mismatch between coarse and fine varactor tuning devices within a segmented unified varactor bank of a radio frequency (RF) digitally controlled oscillator (DCO). The DCO uses a single unified bank of varactors that is divided into an MSB bank, LSB bank and sigma-delta (SD-LSB) bank. Any ratio mismatches between MSBs and LSBs are digitally calibrated out using a DCO step-size pre-distortion scheme wherein the LSB steps are adjusted to account for the ratio mismatch between the MSB/LSB step sizes. A harmonic characterization technique is used to estimate the mismatches in the minimal size CMOS tuning varactors of a digitally controlled RF oscillator (DCO), wherein the nominal ratio mismatch between the MSB and LSB devices is estimated using hybrid stochastic gradient DCO gain estimation algorithms. The nominal ratio mismatch and the mismatches in the MSB and LSB banks are used to determine the average MSB/LSB mismatch. The average mismatch value is then used to correct the LSB steps.
摘要翻译：一种用于射频（RF）数字控制振荡器（DCO）的分段式统一变容管组内的粗调和精细变容二极管调谐装置之间的器件失配的谐波表征和比率校正的新型装置和方法。 DCO使用分为MSB库，LSB库和Σ-Δ（SD-LSB）库的单个统一的变容二极管组。使用DCO步长预失真方案对MSB和LSB之间的任何比例不匹配进行数字校准，其中LSB步长被调整以考虑MSB / LSB步长之间的比率失配。使用谐波表征技术来估计数字控制RF振荡器（DCO）的最小尺寸CMOS调谐变容二极管中的不匹配，其中使用混合随机梯度DCO增益估计算法来估计MSB和LSB器件之间的标称比率失配。标称比例失配和MSB和LSB组中的不匹配用于确定平均MSB / LSB失配。然后使用平均不匹配值来校正LSB步长。

10. 发明授权

US08170507B2 Predistortion methods and apparatus for transmitter linearization in a communication transceiver 有权
标题翻译：用于通信收发器中发射机线性化的预失真方法和装置
公开(公告)号：US08170507B2
公开(公告)日：2012-05-01
申请号：US12260832
申请日：2008-10-29
申请人： Yongtao Wang , Khurram Waheed , Sameh S. Rezeq , Jaimin Mehta , Prasad Srinivasan , Khurram Muhammad
发明人： Yongtao Wang , Khurram Waheed , Sameh S. Rezeq , Jaimin Mehta , Prasad Srinivasan , Khurram Muhammad
IPC分类号： H04B1/04
CPC分类号： H03F3/24 , H03F1/3241 , H03F3/72 , H04B2001/0425
摘要： Predistortion methods and apparatus for transmitter linearization in a communication transceiver are disclosed. An example apparatus to linearize a digitally controlled pre-power amplifier included in a transmitter of a communication transceiver disclosed herein comprises a predistorter to predistort an input signal to be processed by the digitally controlled pre-power amplifier, a coupling path within the communication transceiver to couple an output of the digitally controlled pre-power amplifier to an input of a receiver included in the communication transceiver without enabling an output power amplifier stage of a multi-stage power amplifier coupled to an output of the digitally controlled pre-power amplifier, wherein no additional hardware components are required to implement the coupling path within the communication transceiver, and a predistortion evaluator comprising a predistortion calibrator and a predistortion compensator to process data demodulated by the receiver to generate and update predistortion values for use by the predistorter.
摘要翻译：公开了用于通信收发器中的发射机线性化的预失真方法和装置。线性化包括在本文公开的通信收发器的发射机中的数字控制的预功率放大器的示例性装置包括预失真器，用于预失真由数字控制的预功率放大器处理的输入信号，通信收发器内的耦合路径将数字控制的预功率放大器的输出耦合到通信收发器中包括的接收器的输入，而不使能耦合到数字控制的预功率放大器的输出的多级功率放大器的输出功率放大器级，其中不需要额外的硬件组件来实现通信收发信机内的耦合路径，以及预失真评估器，包括预失真校准器和预失真补偿器，用于处理由接收机解调的数据，以生成和更新预失真值供预失真器使用。

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