专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08343716B2 Method of forming variable patterns using a reticle 有权
标题翻译：使用掩模版形成可变图案的方法
公开(公告)号：US08343716B2
公开(公告)日：2013-01-01
申请号：US12253025
申请日：2008-10-16
申请人： Lee J. Jacobson , Francis J. McNally , Zualfquar Mohammed , Robert Maher
发明人： Lee J. Jacobson , Francis J. McNally , Zualfquar Mohammed , Robert Maher
IPC分类号： G03C5/04
CPC分类号： G03F7/70425 , G03F7/70541
摘要： A method of forming a variable pattern across a wafer using a reticle forms a plurality of first patterns on the wafer. The first pattern is repeated across the wafer and each first pattern has a first readable element. The method also forms a plurality of second patterns on the wafer. The second patterns is repeated across the wafer and each second pattern has a second readable element. The second patterns are positioned relative to the first patterns by aligning a first second pattern relative to one portion of a corresponding first pattern and then incrementally misaligning each successive second pattern in a row or a column relative to its corresponding first pattern. Thus, each corresponding first readable element and second readable element form a corresponding variable pattern.
摘要翻译：使用掩模版在晶片上形成可变图案的方法在晶片上形成多个第一图案。跨晶片重复第一图案，并且每个第一图案具有第一可读元件。该方法还在晶片上形成多个第二图案。跨晶片重复第二图案，并且每个第二图案具有第二可读元件。通过使相对于对应的第一图案的一个部分相对于第一第二图案然后相对于其对应的第一图案逐行地将每个连续的第二图案与行或列相对错位，使第二图案相对于第一图案定位。因此，每个对应的第一可读元素和第二可读元素形成对应的可变模式。

2. 发明申请

US20090098487A1 Method of Forming Variable Patterns Using a Reticle 有权
标题翻译：使用光罩形成可变图案的方法
公开(公告)号：US20090098487A1
公开(公告)日：2009-04-16
申请号：US12253025
申请日：2008-10-16
申请人： Lee J. Jacobson , Francis J. McNally , Zualfquar Mohammed , Robert Maher
发明人： Lee J. Jacobson , Francis J. McNally , Zualfquar Mohammed , Robert Maher
IPC分类号： G03F7/20
CPC分类号： G03F7/70425 , G03F7/70541
摘要： A method of forming a variable pattern across a wafer using a reticle forms a plurality of first patterns on the wafer. The first pattern is repeated across the wafer and each first pattern has a first readable element. The method also forms a plurality of second patterns on the wafer. The second patterns is repeated across the wafer and each second pattern has a second readable element. The second patterns are positioned relative to the first patterns by aligning a first second pattern relative to one portion of a corresponding first pattern and then incrementally misaligning each successive second pattern in a row or a column relative to its corresponding first pattern. Thus, each corresponding first readable element and second readable element form a corresponding variable pattern.
摘要翻译：使用掩模版在晶片上形成可变图案的方法在晶片上形成多个第一图案。跨晶片重复第一图案，并且每个第一图案具有第一可读元件。该方法还在晶片上形成多个第二图案。跨晶片重复第二图案，并且每个第二图案具有第二可读元件。通过使相对于对应的第一图案的一个部分相对于第一第二图案然后相对于其对应的第一图案逐行地将每个连续的第二图案与行或列相对错位，使第二图案相对于第一图案定位。因此，每个对应的第一可读元素和第二可读元素形成对应的可变模式。

3. 发明授权

US07900076B2 Power management method for a pipelined computer system 失效
标题翻译：流水线计算机系统的电源管理方法
公开(公告)号：US07900076B2
公开(公告)日：2011-03-01
申请号：US11932160
申请日：2007-10-31
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A power management method for a pipelined computer system in accordance with one or both of a power management signal and a power management instruction.
摘要翻译：根据电源管理信号和电源管理指令中的一个或两个的流水线计算机系统的电源管理方法。

4. 发明申请

US20060227758A1 Apparatus and method creating virtual routing domains in an internet protocol network 有权
标题翻译：在互联网协议网络中创建虚拟路由域的装置和方法
公开(公告)号：US20060227758A1
公开(公告)日：2006-10-12
申请号：US11103099
申请日：2005-04-09
申请人： Ashwin Rana , Milton Lie , Robert Walls , Robert Maher
发明人： Ashwin Rana , Milton Lie , Robert Walls , Robert Maher
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/302 , H04L45/04 , H04L45/3065 , H04L45/38 , H04L47/10 , H04L47/20 , H04L47/2416 , H04L47/2425 , H04L47/6215 , H04L63/0272 , H04L63/1458
摘要： A method and apparatus is described that allow the creation of virtual routing domains in an IP network. These virtual routing domains allow individual networks to be configures so that it appears that its routing domain covers the entire IP address space. A network processing system is used to implement the virtual routing domains and to allow network traffic to cross the individual routing domains. The network processing system is able to use application layer information to allow the crossing of virtual routing domain boundaries. By examining application layer information the network processing system is able to look up customer/user information and use that information to determine destination virtual routing domains and route otherwise unroutable addresses between domains.
摘要翻译：描述了允许在IP网络中创建虚拟路由域的方法和装置。这些虚拟路由域允许单独的网络进行配置，以使它的路由域覆盖整个IP地址空间。网络处理系统用于实现虚拟路由域，并允许网络流量跨越各个路由域。网络处理系统能够使用应用层信息来允许跨越虚拟路由域边界。通过检查应用层信息，网络处理系统能够查找客户/用户信息，并使用该信息来确定目的地虚拟路由域，并在域间路由否则不可路由的地址。

5. 发明授权

US07000132B2 Signal-initiated power management method for a pipelined data processor 失效
标题翻译：用于流水线数据处理器的信号发起的电源管理方法
公开(公告)号：US07000132B2
公开(公告)日：2006-02-14
申请号：US10784396
申请日：2004-02-23
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G08F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A signal-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to at least one control signal.
摘要翻译：一种用于流水线数据处理器的信号发起的功率管理方法，通过该方式，响应于至少一个控制信号选择性地禁用对管道子电路的时钟信号。

6. 发明授权

US06694443B1 SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE TO CONDITION ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY 失效
标题翻译：通过对微处理器的控制信号进行控制和去除控制信号来控制微处理器的功率的系统，该控制信号响应于微处理器进入和退出低功率状态的条件
公开(公告)号：US06694443B1
公开(公告)日：2004-02-17
申请号：US09779150
申请日：2001-02-08
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F130
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Power consumption reduction control circuitry external and coupled to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.
摘要翻译：功耗降低控制电路外部并耦合到用于执行用于数据处理的指令的处理器。电源管理控制信号根据处理器在正常和降低的功耗操作模式下运行的条件提供给处理器，并且指示这种降低的功耗模式的确认信号对应于功率管理控制信号。

7. 发明授权

US07120810B2 Instruction-initiated power management method for a pipelined data processor 失效
标题翻译：用于流水线数据处理器的指令启动的电源管理方法
公开(公告)号：US07120810B2
公开(公告)日：2006-10-10
申请号：US10784846
申请日：2004-02-23
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry.
摘要翻译：一种用于流水线数据处理器的指令发起的电源管理方法，通过该电源管理方法，响应于由管道子电路执行的指令，选择性地禁用对管道子电路的时钟信号。

8. 发明申请

US20060085548A1 Apparatus and method for firewall traversal 有权
标题翻译：防火墙穿越的装置和方法
公开(公告)号：US20060085548A1
公开(公告)日：2006-04-20
申请号：US10967470
申请日：2004-10-18
申请人： Robert Maher , Aswinkumar Rana , Milton Lie , James Deerman
发明人： Robert Maher , Aswinkumar Rana , Milton Lie , James Deerman
IPC分类号： G06F15/16
CPC分类号： H04L63/029 , H04L29/06027 , H04L65/1006
摘要： An apparatus and method for traversing a network address translation/firewall device to maintain a registration between first and second devices separated by the firewall device are provided. In one example, the method includes intercepting a registration message from the first device to the second device. A determination is made based on a first timeout period defined by the second device as to whether it is time to renew the first device's registration. If it is time to renew the first device's registration, the registration message is forwarded to the second device. A response message that includes the first timeout period is intercepted, and the first timeout period is replaced with a second timeout period based on a binding lifetime of the firewall device before forwarding the response message to the first device.
摘要翻译：提供了一种用于遍历网络地址转换/防火墙设备以维护由防火墙设备分离的第一和第二设备之间的注册的装置和方法。在一个示例中，该方法包括从第一设备截取注册消息到第二设备。基于由第二设备定义的关于是否需要续订第一设备的注册的第一超时时段进行确定。如果是更新第一个设备的注册的时间，则注册消息被转发到第二个设备。拦截包含第一超时期间的响应消息，并且在将响应消息转发给第一设备之前，基于防火墙设备的绑定寿命，第一超时时段被替换为第二超时时段。

9. 发明授权

US06721894B2 METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE CONDITIONS ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY 失效
标题翻译：通过在与微处理器相关的响应条件下通过对微控制器的控制信号进行控制和去除控制信号来控制微处理器的功率的方法进入和退出低功率状态
公开(公告)号：US06721894B2
公开(公告)日：2004-04-13
申请号：US10216615
申请日：2002-08-09
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F126
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： In accordance with the presently claimed invention, power consumption reduction control is provided to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.
摘要翻译：根据目前要求保护的发明，将功耗降低控制提供给用于执行用于数据处理的指令的处理器。电源管理控制信号根据处理器在正常和降低的功耗操作模式下运行的条件提供给处理器，并且指示这种降低的功耗模式的确认信号对应于功率管理控制信号。

10. 发明授权

US06343363B1 Method of invoking a low power mode in a computer system using a halt instruction 有权
标题翻译：使用停止指令在计算机系统中调用低功耗模式的方法
公开(公告)号：US06343363B1
公开(公告)日：2002-01-29
申请号：US09570155
申请日：2000-05-12
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F132
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. In a preferred embodiment, the low power operational mode is entered by stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.
摘要翻译：在包括耦合到外部逻辑的处理器的计算机系统中使用用于响应于停止指令来调用低功率操作模式的技术。处理器至少包括（i）用于执行编程指令的管道子电路，包括停止指令，（ii）中断处理子电路以处理由外部中断逻辑产生的中断;以及（iii）向管线提供时钟信号的时钟发生器电路和中断处理子电路。响应于停止指令的执行，处理器（i）至少输入管道子电路而进入功率消耗降低的低功率操作模式，但不停止向中断处理子电路提供时钟信号，并且（ii ）向外部逻辑产生一个确认信号，指示管道子电路的时钟信号正在停止，从而进入低功率操作模式。在优选实施例中，通过停止时钟发生器电路将时钟信号提供给管道子电路而不是中断处理子电路来进入低功率操作模式。为了恢复正常处理，中断处理子电路通过使时钟发生器电路恢复向管道子电路提供时钟信号，来响应由外部逻辑产生的中断。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式