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1. 发明授权

US07120810B2 Instruction-initiated power management method for a pipelined data processor 失效
标题翻译：用于流水线数据处理器的指令启动的电源管理方法
公开(公告)号：US07120810B2
公开(公告)日：2006-10-10
申请号：US10784846
申请日：2004-02-23
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry.
摘要翻译：一种用于流水线数据处理器的指令发起的电源管理方法，通过该电源管理方法，响应于由管道子电路执行的指令，选择性地禁用对管道子电路的时钟信号。

2. 发明授权

US06721894B2 METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE CONDITIONS ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY 失效
标题翻译：通过在与微处理器相关的响应条件下通过对微控制器的控制信号进行控制和去除控制信号来控制微处理器的功率的方法进入和退出低功率状态
公开(公告)号：US06721894B2
公开(公告)日：2004-04-13
申请号：US10216615
申请日：2002-08-09
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F126
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： In accordance with the presently claimed invention, power consumption reduction control is provided to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.
摘要翻译：根据目前要求保护的发明，将功耗降低控制提供给用于执行用于数据处理的指令的处理器。电源管理控制信号根据处理器在正常和降低的功耗操作模式下运行的条件提供给处理器，并且指示这种降低的功耗模式的确认信号对应于功率管理控制信号。

3. 发明授权

US06343363B1 Method of invoking a low power mode in a computer system using a halt instruction 有权
标题翻译：使用停止指令在计算机系统中调用低功耗模式的方法
公开(公告)号：US06343363B1
公开(公告)日：2002-01-29
申请号：US09570155
申请日：2000-05-12
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F132
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. In a preferred embodiment, the low power operational mode is entered by stopping the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.
摘要翻译：在包括耦合到外部逻辑的处理器的计算机系统中使用用于响应于停止指令来调用低功率操作模式的技术。处理器至少包括（i）用于执行编程指令的管道子电路，包括停止指令，（ii）中断处理子电路以处理由外部中断逻辑产生的中断;以及（iii）向管线提供时钟信号的时钟发生器电路和中断处理子电路。响应于停止指令的执行，处理器（i）至少输入管道子电路而进入功率消耗降低的低功率操作模式，但不停止向中断处理子电路提供时钟信号，并且（ii ）向外部逻辑产生一个确认信号，指示管道子电路的时钟信号正在停止，从而进入低功率操作模式。在优选实施例中，通过停止时钟发生器电路将时钟信号提供给管道子电路而不是中断处理子电路来进入低功率操作模式。为了恢复正常处理，中断处理子电路通过使时钟发生器电路恢复向管道子电路提供时钟信号，来响应由外部逻辑产生的中断。

4. 发明授权

US6088807A Computer system with low power mode invoked by halt instruction 失效
标题翻译：通过暂停指令调用低功耗模式的计算机系统
公开(公告)号：US6088807A
公开(公告)日：2000-07-11
申请号：US777772
申请日：1996-12-09
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F1/32 , G06F9/30 , G06F9/38 , G06F13/40
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3287 , G06F13/4072 , G06F9/3869 , Y02B60/1221 , Y02B60/1235 , Y02B60/1282
摘要： A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode. To resume normal processing, the interrupt handling subcircuit responds to an interrupt generated by the external logic by causing the clock generator circuitry to resume supplying clock signals to the pipeline subcircuit.
摘要翻译：在包括耦合到外部逻辑的处理器的计算机系统中使用用于响应于停止指令来调用低功率操作模式的技术。处理器至少包括（i）用于执行编程指令的管道子电路，包括停止指令，（ii）中断处理子电路以处理由外部中断逻辑产生的中断;以及（iii）向管线提供时钟信号的时钟发生器电路和中断处理子电路。响应于停止指令的执行，处理器（i）停止时钟发生器电路向管道子电路提供时钟信号，而不是中断处理子电路，并且（ii）向外部逻辑产生一个确认信号，指示该到管道子电路的时钟信号正在停止，从而进入低功率操作模式。为了恢复正常处理，中断处理子电路通过使时钟发生器电路恢复向管道子电路提供时钟信号，来响应由外部逻辑产生的中断。

5. 发明授权

US07900076B2 Power management method for a pipelined computer system 失效
标题翻译：流水线计算机系统的电源管理方法
公开(公告)号：US07900076B2
公开(公告)日：2011-03-01
申请号：US11932160
申请日：2007-10-31
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A power management method for a pipelined computer system in accordance with one or both of a power management signal and a power management instruction.
摘要翻译：根据电源管理信号和电源管理指令中的一个或两个的流水线计算机系统的电源管理方法。

6. 发明授权

US07000132B2 Signal-initiated power management method for a pipelined data processor 失效
标题翻译：用于流水线数据处理器的信号发起的电源管理方法
公开(公告)号：US07000132B2
公开(公告)日：2006-02-14
申请号：US10784396
申请日：2004-02-23
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G08F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A signal-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to at least one control signal.
摘要翻译：一种用于流水线数据处理器的信号发起的功率管理方法，通过该方式，响应于至少一个控制信号选择性地禁用对管道子电路的时钟信号。

7. 发明授权

US06694443B1 SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE TO CONDITION ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY 失效
标题翻译：通过对微处理器的控制信号进行控制和去除控制信号来控制微处理器的功率的系统，该控制信号响应于微处理器进入和退出低功率状态的条件
公开(公告)号：US06694443B1
公开(公告)日：2004-02-17
申请号：US09779150
申请日：2001-02-08
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F130
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Power consumption reduction control circuitry external and coupled to a processor used to execute instructions for data processing. A power management control signal is provided to the processor in accordance with conditions associated with the processor being operated in normal and reduced power consumption modes of operation, and an acknowledgement signal indicative of such reduced power consumption mode of operation is returned in correspondence with the power management control signal.
摘要翻译：功耗降低控制电路外部并耦合到用于执行用于数据处理的指令的处理器。电源管理控制信号根据处理器在正常和降低的功耗操作模式下运行的条件提供给处理器，并且指示这种降低的功耗模式的确认信号对应于功率管理控制信号。

8. 发明授权

US5664149A Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol 失效
标题翻译：使用导出/无效协议设计用于直写缓存的系统中的回写缓存的一致性
公开(公告)号：US5664149A
公开(公告)日：1997-09-02
申请号：US151489
申请日：1993-11-12
申请人： Marvin Wayne Martinez, Jr. , Mark W. Bluhm , Jeffrey S. Byrne , David A. Courtright , Douglas Ewing Duschatko , Raul A. Garibay, Jr. , Margaret R. Herubin
发明人： Marvin Wayne Martinez, Jr. , Mark W. Bluhm , Jeffrey S. Byrne , David A. Courtright , Douglas Ewing Duschatko , Raul A. Garibay, Jr. , Margaret R. Herubin
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0804 , G06F12/0808 , G06F12/0831 , G06F12/0835
摘要： A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i.e., if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.
摘要翻译：在示例性实施例中，在计算机系统中使用的微处理器中使用包括FLUSH / INVAL和LOCK协议的回写一致性系统，其选择性地向处理器提供FLUSH和INVAL信号以实现有限的回写协议。计算机系统使用FLUSH / INVAL协议来控制导出和无效操作。响应于FLUSH信号，微处理器从缓存中导出脏数据。如果INVAL也被置位，则高速缓存也被无效（即，如果FLUSH被断言且INVAL未被置位，则不执行无效）。使用LOCK协议，LOCK读取从高速缓存中进行读取命中，但是为了保持与计算机系统的兼容性，这些计算机系统期望LOCK操作涉及读取，然后对外部存储器进行写访问，微处理器仍然会运行外部锁定的读取周期，忽略返回的数据。

9. 发明授权

US07509512B2 Instruction-initiated method for suspending operation of a pipelined data processor 失效
标题翻译：用于暂停流水线数据处理器操作的指令启动方法
公开(公告)号：US07509512B2
公开(公告)日：2009-03-24
申请号：US10784702
申请日：2004-02-23
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： An instruction-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to an instruction executed by the pipeline subcircuitry.
摘要翻译：一种指令启动的方法，用于通过选择性地禁用时钟信号来管理流水线数据处理器，以响应于由管道子电路执行的指令来管理子电路。

10. 发明授权

US07062666B2 Signal-initiated method for suspending operation of a pipelined data processor 失效
标题翻译：用于暂停流水线数据处理器操作的信号发起方法
公开(公告)号：US07062666B2
公开(公告)日：2006-06-13
申请号：US10784834
申请日：2004-02-23
申请人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
发明人： Robert Maher , Raul A. Garibay, Jr. , Margaret R. Herubin , Mark Bluhm
IPC分类号： G06F1/26
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F9/3867 , G06F9/3869 , G06F13/4072 , Y02D10/128 , Y02D10/151 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： A signal-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to at least one control signal.
摘要翻译：一种用于通过响应于至少一个控制信号选择性地禁用时钟信号来流水线分流来暂停流水线数据处理器的操作的信号发起的方法。

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