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1. 发明授权

US08404585B2 Preventing breakage of long metal signal conductors on semiconductor substrates 有权
标题翻译：防止半导体基板上的长金属信号导体断裂
公开(公告)号：US08404585B2
公开(公告)日：2013-03-26
申请号：US13135510
申请日：2011-07-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L21/44
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigaPascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.
摘要翻译：一种装置包括设置在半导体衬底的顶表面上的绝缘体体积，软电介质管和金属导体。绝缘体具有大于约3千兆帕（gPa）的硬度，软电介质具有小于3gPa的硬度。软电介质管和金属导体都嵌入在绝缘体的体积内。管限定中心体积，并且金属导体沿着穿过中心体积的方向延伸至少一英寸的距离。当在垂直于该方向的横截面中观察装置时，金属导体被软电介质环绕。金属导体可以包括多个弯曲部分。当设备在零度至摄氏度摄氏八十度的范围内温度循环时，金属导体不会断裂。

2. 发明授权

US08099691B1 Disabling unused/inactive resources in an integrated circuit for static power reduction 有权
标题翻译：禁用集成电路中的未使用/不活动资源以实现静态功耗降低
公开(公告)号：US08099691B1
公开(公告)日：2012-01-17
申请号：US12491174
申请日：2009-06-24
申请人： Tim Tuan , Kameswara K. Rao , Robert O. Conn
发明人： Tim Tuan , Kameswara K. Rao , Robert O. Conn
IPC分类号： G06F17/50
CPC分类号： H03K19/17784
摘要： A method of operating an integrated circuit (“IC”) is disclosed. The method includes identifying one or more unused or inactive resources of the IC which will not be used in a circuit design or which are inactive during operation of the IC. The method also includes enabling resources of the IC which will be used in the circuit design, and also disabling one or more unused or inactive resources of the IC from one or more power supply terminals in response to configuration values which are stored in memory cells.
摘要翻译：公开了一种操作集成电路（“IC”）的方法。该方法包括识别不在电路设计中使用的IC中的一个或多个未使用或非活动资源，或者在IC运行期间不活动的资源。该方法还包括启用将用于电路设计中的IC的资源，以及响应于存储在存储单元中的配置值，从一个或多个电源端子禁用IC的一个或多个未使用或不活动的资源。

3. 发明授权

US07944041B2 Integrated semiconductor substrate structure using incompatible processes 有权
公开(公告)号：US07944041B2
公开(公告)日：2011-05-17
申请号：US11975966
申请日：2007-10-22
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/52
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material.

4. 发明申请

US20100187665A1 Integral metal structure with conductive post portions 有权
标题翻译：具有导电柱部分的整体金属结构
公开(公告)号：US20100187665A1
公开(公告)日：2010-07-29
申请号：US12321833
申请日：2009-01-26
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/48 , H01L21/302 , H01L21/31
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.
摘要翻译：多个FPGA管芯设置在半导体衬底上。为了提供多个FPGA芯片所需的巨大功率，功率从位于半导体衬底另一侧的厚金属层和大的整体金属结构垂直地穿过半导体衬底。由于半导体衬底与与衬底接触的金属层具有不同的热线性膨胀系数，所以当结构经受温度变化时，可能发生分层。为了防止与半导体衬底连接并与整体金属结构电接触的金属层的分层，整体金属结构被制成具有一定数量的柱部分。在温度变化期间，整体金属结构的后部相对于连接到半导体衬底的金属层弯曲和滑动，并且防止否则会引起分层的线性应力。

5. 发明授权

US07719844B2 Stackable self-aligning insulative guide tray for holding semiconductor substrates 有权
标题翻译：用于保持半导体衬底的可堆叠自对准绝缘导板
公开(公告)号：US07719844B2
公开(公告)日：2010-05-18
申请号：US11999747
申请日：2007-12-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： G06F1/16
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A reconfigurable high performance computer includes a stack of self-aligning, injection-molded plastic, insulative guide trays. Each insulative guide tray retains at least one semiconductor substrate assembly (SSA) in a lateral dimension with respect to a set of elastomeric connectors. The trays hold the SSAs and the elastomeric connectors such that the elastomeric connectors are sandwiched between, and interconnect, adjacent semiconductor substrates proceeding down the stack. The trays also hold comb-shaped power bus bar assemblies such that power bus bars contact and supply power to circuitry of the SSAs of the stack.
摘要翻译：可重新配置的高性能计算机包括一堆自对准，注塑塑料，绝缘导向盘。每个绝缘引导托盘相对于一组弹性体连接器在侧向尺寸上保持至少一个半导体衬底组件（SSA）。托盘固定SSA和弹性体连接器，使得弹性体连接器夹在相邻的半导体衬底之间并互连在堆叠之上。托盘还保持梳状电力汇流条组件，使得电力母线与电池堆的SSA的电路接触并供电。

6. 发明授权

US07667473B1 Flip-chip package having thermal expansion posts 有权
标题翻译：具有热膨胀柱的倒装芯片封装
公开(公告)号：US07667473B1
公开(公告)日：2010-02-23
申请号：US11238419
申请日：2005-09-28
申请人： Robert O. Conn , Steven J. Carey
发明人： Robert O. Conn , Steven J. Carey
IPC分类号： G01R31/02
CPC分类号： H01L23/10 , H01L21/563 , H01L23/3128 , H01L23/3675 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/0554 , H01L2224/05572 , H01L2224/05573 , H01L2224/10175 , H01L2224/13016 , H01L2224/131 , H01L2224/13147 , H01L2224/16057 , H01L2224/16225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81193 , H01L2224/81385 , H01L2224/814 , H01L2224/81447 , H01L2224/81815 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19041 , H01L2924/014 , H01L2924/01014 , H01L2924/00 , H01L2924/3512 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package having a substrate and a die includes a plurality of conductive posts attached to the substrate and bonded to an active surface of the die via a plurality of corresponding microbumps. The conductive posts are flexible and extend beyond the top surface of the substrate a sufficient distance to absorb lateral forces exerted upon the microbumps.
摘要翻译：具有基板和模具的半导体封装包括附接到基板的多个导电柱，并且经由多个相应的微凸块结合到模具的有效表面。导电柱是柔性的并且延伸超过基板的顶表面足够的距离以吸收施加在微胶片上的横向力。

7. 发明申请

US20090267183A1 Through-substrate power-conducting via with embedded capacitance 审中-公开
标题翻译：具有嵌入式电容的通过衬底的导电通孔
公开(公告)号：US20090267183A1
公开(公告)日：2009-10-29
申请号：US12150529
申请日：2008-04-28
申请人： Dorota Temple , Robert O. Conn
发明人： Dorota Temple , Robert O. Conn
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/481 , H01L21/76898 , H01L2224/05568 , H01L2224/05573 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/014 , H01L2224/05599
摘要： When integrated circuits are mounted on a substrate, little space is often available for the required large number of bypass capacitors. A novel substrate structure therefore includes many closely spaced through-holes that extend from a first surface of the substrate to a second surface of the substrate. Each through-hole includes a first conducting layer, a dielectric layer, and a second conducting layer. The first and second conducting layers and the intervening dielectric layer constitute a via having a substantial capacitance (one picofarad). Some of the many vias provide bypass capacitance directly under the integrated circuits. A first set of vias supplies power from a power bus bar on one side of the substrate to the integrated circuits on the other side. A second set of vias sinks current from the integrated circuits on the other side, through the substrate, and to a ground bus bar on the one side.
摘要翻译：当集成电路安装在基板上时，通常对所需的大量旁路电容器几乎没有空间。因此，新颖的衬底结构包括从衬底的第一表面延伸到衬底的第二表面的许多紧密间隔的通孔。每个通孔包括第一导电层，电介质层和第二导电层。第一和第二导电层和介入介电层构成具有相当大电容（一个皮法）的通孔。许多通孔中的一些直接在集成电路下提供旁路电容。第一组通孔从基板一侧的电源母线供给另一侧的集成电路。第二组通孔从另一侧的集成电路，通过基板和一侧的接地母线吸收电流。

8. 发明授权

US07549139B1 Tuning programmable logic devices for low-power design implementation 有权
标题翻译：调整可编程逻辑器件，实现低功耗设计
公开(公告)号：US07549139B1
公开(公告)日：2009-06-16
申请号：US10783216
申请日：2004-02-20
申请人： Tim Tuan , Jan L. deJong , Kameswara K. Rao , Robert O. Conn
发明人： Tim Tuan , Jan L. deJong , Kameswara K. Rao , Robert O. Conn
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： H03K19/17784 , G11C5/14 , H03K3/356173 , H03K19/0016 , H03K19/17792
摘要： A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.
摘要翻译：一种操作可编程逻辑器件的方法包括以下步骤：使用完整的VDD电源电压来操作可编程逻辑器件的第一组有源块，并使用降低的电源电压（例如，0.9Vd）来操作第二组可编程逻辑器件的有源块。执行时序分析以确定每个活动块中的最大可用时序松弛。具有较小定时松弛的有源块被分组在第一组中，并且被耦合以接收完整的VDD电源电压。具有较大定时松弛的有源块被分组在第二组中，并被耦合以接收降低的VDD电源电压。结果，第二组中的活动块表现出降低的功耗，而不会对可编程逻辑器件的总速度产生不利影响。

9. 发明申请

US20090080152A1 Stackable self-aligning insulative guide tray for holding semiconductor substrates 有权
标题翻译：用于保持半导体衬底的可堆叠自对准绝缘导板
公开(公告)号：US20090080152A1
公开(公告)日：2009-03-26
申请号：US11999747
申请日：2007-12-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H05K7/02 , H05K7/20 , A47B81/00 , H05K7/00
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A reconfigurable high performance computer includes a stack of self-aligning, injection-molded plastic, insulative guide trays. Each insulative guide tray retains at least one semiconductor substrate assembly (SSA) in a lateral dimension with respect to a set of elastomeric connectors. The trays hold the SSAs and the elastomeric connectors such that the elastomeric connectors are sandwiched between, and interconnect, adjacent semiconductor substrates proceeding down the stack. The trays also hold comb-shaped power bus bar assemblies such that power bus bars contact and supply power to circuitry of the SSAs of the stack.
摘要翻译：可重新配置的高性能计算机包括一堆自对准，注塑塑料，绝缘导向盘。每个绝缘引导托盘相对于一组弹性体连接器在侧向尺寸上保持至少一个半导体衬底组件（SSA）。托盘固定SSA和弹性体连接器，使得弹性体连接器夹在相邻的半导体衬底之间并互连在堆叠之上。托盘还保持梳状电力汇流条组件，使得电力母线与电池堆的SSA的电路接触并供电。

10. 发明授权

US07233061B1 Interposer for impedance matching 有权
标题翻译：用于阻抗匹配的插入器
公开(公告)号：US07233061B1
公开(公告)日：2007-06-19
申请号：US10698906
申请日：2003-10-31
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/02
CPC分类号： H01L23/50 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/66 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/16265 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/81143 , H01L2224/8121 , H01L2224/81815 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/09701 , H01L2924/10253 , H01L2924/12036 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/19011 , H01L2924/19041 , H01L2924/19103 , H01L2924/30107 , H01L2924/3011 , H05K1/0231 , H05K1/0237 , H05K1/141 , H05K1/142 , H05K1/162 , H05K3/3436 , H05K2201/09309 , H05K2201/10378 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.
摘要翻译：电容插入器（caposer）设置在芯片与封装的内表面之间的集成电路封装内。钳口内的导电层构成旁路电容器。在通孔捕获器中，裸片上的微型凸块通过钳口中的通孔并与封装上相应的着陆焊盘接触。当电容和接地微型突起通过电容器时，接触旁路电容器的电极。在通孔容量中，芯片上的电源和接地微型突起通过电源和接地通孔耦合到封装上的电源和接地焊盘以及旁路电容器的板上，延伸通过钳口。在信号再分配电容器中，钳位器内的导体在管芯微突起和封装着陆焊盘之间重新分配信号。在阻抗匹配钳位器中，钳位器内的端接结构为印刷电路板迹线提供阻抗匹配。

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