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1. 发明授权

US07557624B2 Fractional digital PLL 有权
标题翻译：小数字数字PLL
公开(公告)号：US07557624B2
公开(公告)日：2009-07-07
申请号：US11940458
申请日：2007-11-15
申请人： Robertus Laurentius van der Valk , Paulus Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
发明人： Robertus Laurentius van der Valk , Paulus Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/091 , H03L7/0991 , H03L7/18 , H03L2207/10 , H03L2207/50
摘要： A phase locked loop provides an output frequency that bears a fractional relationship to an input frequency and includes a controlled oscillator for generating the output frequency. The phase information is scaled in the amplitude domain to provide the fractional relationship.
摘要翻译：锁相环提供与输入频率成分关系的输出频率，并且包括用于产生输出频率的受控振荡器。相位信息在幅度域中缩放以提供分数关系。

2. 发明授权

US06795520B2 High speed digital counters 失效
标题翻译：高速数字计数器
公开(公告)号：US06795520B2
公开(公告)日：2004-09-21
申请号：US10355903
申请日：2003-01-31
申请人： Robertus Laurentius Van Der Valk
发明人： Robertus Laurentius Van Der Valk
IPC分类号： H03K2116
CPC分类号： H03K23/665 , H03K23/584
摘要： A high speed digital counter consists of a chain of asynchronous counter cells. Each cell includes a flip-flop with a master latch and a slave latch and a clock gating circuit. The clock gating circuit derives an enable input from an output of the master latch.
摘要翻译：高速数字计数器由一系列异步计数器组成。每个单元包括具有主锁存器和从锁存器和时钟门控电路的触发器。时钟门控电路从主锁存器的输出中导出使能输入。

3. 发明申请

US20090184736A1 FLEXIBLE WAVEFORM GENERATOR WITH EXTENDED RANGE CAPABILITY 有权
标题翻译：具有扩展范围能力的柔性波形发生器
公开(公告)号：US20090184736A1
公开(公告)日：2009-07-23
申请号：US12179712
申请日：2008-07-25
申请人： Johannes Hermanus Aloysius De Rijk , Robertus Laurentius van der Valk
发明人： Johannes Hermanus Aloysius De Rijk , Robertus Laurentius van der Valk
IPC分类号： H03B21/00
CPC分类号： G06F1/025
摘要： A frequency synthesizer includes a first clock running at a frequency fCLK1, a second clock running at a frequency fCLK2, wherein frequency fCLK2 is higher than frequency fCLK1, the frequencies having a fixed ratio QFB=fCLK2/fCLK1; and a counter driven by the first clock. A decoder for produces QFB output values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these QFB output values at the frequency of the second clock.
摘要翻译：频率合成器包括以频率fCLK1运行的第一时钟，以频率fCLK2运行的第二时钟，其中频率fCLK2高于频率fCLK1，频率具有固定比率QFB = fCLK2 / fCLK1; 和由第一个时钟驱动的计数器。用于在第一时钟的每个周期并行产生QFB输出值的解码器，并行串行转换器以第二时钟的频率串行输出这些QFB输出值。

4. 发明申请

US20080116982A1 DIGITAL PHASE LOCKED LOOP 有权
标题翻译：数字相位锁定环
公开(公告)号：US20080116982A1
公开(公告)日：2008-05-22
申请号：US11939894
申请日：2007-11-14
申请人： Robertus Laurentius van der Valk , Paulus Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
发明人： Robertus Laurentius van der Valk , Paulus Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
IPC分类号： H03L7/085 , H03L7/08
CPC分类号： H03L7/0991 , H03L7/085 , H03L7/091 , H03L7/18 , H03L2207/50
摘要： A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.
摘要翻译：数字锁相环包括用于产生参考信号的相位的数字表示的相位获取单元，具有从相位获取单元的输出接收数字信号或从相位获取单元的输出导出的数字相位检测器的数字相位检测器，数字环路滤波器对数字相位检测器的输出进行滤波，数字控制振荡器在数字环路滤波器的控制下产生输出信号。数字反馈环路从数字控制振荡器的输出端向数字相位检测器提供第二输入。

5. 发明申请

US20080116980A1 ASYNCHRONOUS PHASE ACQUISITION UNIT WITH DITHERING 有权
标题翻译：异步相位采集单元
公开(公告)号：US20080116980A1
公开(公告)日：2008-05-22
申请号：US11939948
申请日：2007-11-14
申请人： Robertus Laurentius van der Valk , Paulus Hendricus Lodewijk Maria Schram , Douglas Robert Sitch
发明人： Robertus Laurentius van der Valk , Paulus Hendricus Lodewijk Maria Schram , Douglas Robert Sitch
IPC分类号： H03L7/085
CPC分类号： H04L7/0331 , H03L7/0807 , H03L7/0991 , H03L2207/50
摘要： A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.
摘要翻译：数字锁相环包括相位获取单元，其接收采样的输入信号并将其输出应用于数字相位检测器的第一输入端，产生数字输出的数字控制振荡器和耦合数字控制的数字输出的数字输出的反馈路径振荡器到数字域中的数字相位检测器的第二输入。可以异步采样输入信号。

6. 发明授权

US07356036B2 Method providing distribution means for reference clocks across packetized networks 有权
标题翻译：分组网络的参考时钟分配方法
公开(公告)号：US07356036B2
公开(公告)日：2008-04-08
申请号：US10781165
申请日：2004-02-18
申请人： Robertus Laurentius Van Der Valk , Willem L. Repko
发明人： Robertus Laurentius Van Der Valk , Willem L. Repko
IPC分类号： H04L12/28 , H04L7/00 , H04J3/06 , G06F1/12
CPC分类号： H04J3/0664 , H04J3/0641
摘要： Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets to said one or more slave nodes, and a receiver at the slave nodes receives the time-stamped synchronization packets and synchronizes the basis clocks in the slave nodes with the basis clock in the master node. Multiple reference clocks are encoded with respect to the basis clock in the master node to generate numerical information describing the reference clock(s) in relation to the basis clock in the master node. The basis clock in each of the slave node is synchronized to the basis clock in the master node using time-stamped synchronization packets. The one or more reference clocks are recovered at the slave nodes using said numerical information describing the reference clock(s) in relation to the basis clock in the master node.
摘要翻译：公开了一种在分组网络上分发多个参考时钟的方法。分组网络具有主节点和一个或多个从节点，主节点和每个从节点具有基时钟。发送方向所述一个或多个从节点发送时间戳的同步分组，并且从节点处的接收机接收时间戳同步分组，并使从节点中的基时钟与主节点中的基本时钟同步。多个参考时钟相对于主节点中的基本时钟被编码，以产生描述与主节点中的基准时钟相关的参考时钟的数字信息。每个从节点中的基准时钟使用时间戳同步数据包同步到主节点中的基本时钟。使用描述与主节点中的基本时钟相关的参考时钟的数字信息，在从节点处恢复一个或多个参考时钟。

7. 发明授权

US07096243B2 Flexible decimator 失效
公开(公告)号：US07096243B2
公开(公告)日：2006-08-22
申请号：US10348308
申请日：2003-01-21
申请人： Robertus Laurentius Van Der Valk , Johannes Hermanus Aloysius De Rijk
发明人： Robertus Laurentius Van Der Valk , Johannes Hermanus Aloysius De Rijk
IPC分类号： G06F17/17
CPC分类号： H03H17/0664 , H03H17/0226
摘要： A decimator for use in digital signal processing has an input line for receiving a sequence of input samples at a first sampling rate and a first register for accumulating input samples for which the order in the sequence is a power of a predetermined number greater than one. A control unit for outputs samples from the first register at a second sampling rate. Typically accumulates input samples for which the order in the sequence is a not power of the predetermined number so that the first register accumulates input samples for which the order of said sequence is a power of the predetermined number combined with a current accumulated value in the second register.

8. 发明授权

US07728634B2 Flexible waveform generator with extended range capability 有权
标题翻译：具有扩展范围能力的灵活波形发生器
公开(公告)号：US07728634B2
公开(公告)日：2010-06-01
申请号：US12179712
申请日：2008-07-25
申请人： Johannes Hermanus Aloysius De Rijk , Robertus Laurentius van der Valk
发明人： Johannes Hermanus Aloysius De Rijk , Robertus Laurentius van der Valk
IPC分类号： H03B21/00
CPC分类号： G06F1/025
摘要： A frequency synthesizer includes a first clock running at a frequency fCLK1, a second clock running at a frequency fCLK2, wherein frequency fCLK2 is higher than frequency fCLK1, the frequencies having a fixed ratio QFB=fCLK2/fCLK1; and a counter driven by the first clock. A decoder for produces QFB output values in parallel for each cycle of the first clock, and parallel-serial converter serially outputs these QFB output values at the frequency of the second clock.
摘要翻译：频率合成器包括以频率fCLK1运行的第一时钟，以频率fCLK2运行的第二时钟，其中频率fCLK2高于频率fCLK1，频率具有固定比率QFB = fCLK2 / fCLK1; 和由第一个时钟驱动的计数器。用于在第一时钟的每个周期并行产生QFB输出值的解码器，并行串行转换器以第二时钟的频率串行输出这些QFB输出值。

9. 发明授权

US07642862B2 Digital phase locked loop 有权
标题翻译：数字锁相环
公开(公告)号：US07642862B2
公开(公告)日：2010-01-05
申请号：US11939894
申请日：2007-11-14
申请人： Robertus Laurentius van der Valk , Paul Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
发明人： Robertus Laurentius van der Valk , Paul Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
IPC分类号： H03L7/06
CPC分类号： H03L7/0991 , H03L7/085 , H03L7/091 , H03L7/18 , H03L2207/50
摘要： A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.
摘要翻译：数字锁相环包括用于产生参考信号的相位的数字表示的相位获取单元，具有从相位获取单元的输出接收数字信号或从相位获取单元的输出导出的数字相位检测器的数字相位检测器，数字环路滤波器对数字相位检测器的输出进行滤波，数字控制振荡器在数字环路滤波器的控制下产生输出信号。数字反馈环路从数字控制振荡器的输出端向数字相位检测器提供第二输入。

10. 发明授权

US07376156B2 Alignment of clocks over multiple packet networks 有权
标题翻译：多个分组网络上的时钟对齐
公开(公告)号：US07376156B2
公开(公告)日：2008-05-20
申请号：US10781510
申请日：2004-02-18
申请人： Willem L. Repko , Robertus Laurentius Van Der Valk , Petrus W. Simons
发明人： Willem L. Repko , Robertus Laurentius Van Der Valk , Petrus W. Simons
IPC分类号： H04J3/06
CPC分类号： H04J3/0673 , H04J3/0664
摘要： Disclosed is a method of aligning clocks over multiple networks having different clock domains. The method comprises transmitting timestamped packets over said networks between source and destination nodes, said timestamped packets conveying timing information based on a source clock at said source node, determining the expected delay over multiple nodes for a given traffic density, identifying at least one intermediate node between said source and destination node where said determined expected delay is such as to permit clock restoration within predefined acceptable parameters, restoring said source clock at said at least one intermediate restoration node to generate a restored intermediate clock signal, producing from said restored intermediate clock signal new timestamped packets conveying timing information based on said restored intermediate clock signal, and forwarding said new timestamped packets to said destination node.
摘要翻译：公开了一种在具有不同时钟域的多个网络上对准时钟的方法。所述方法包括在源节点和目的节点之间通过所述网络传输时间戳分组，所述时间戳分组基于所述源节点处的源时钟传送定时信息，为给定业务密度确定多个节点上的预期延迟，识别至少一个中间节点在所述源和目的地节点之间，其中所述确定的预期延迟使得允许在预定义的可接受参数内的时钟恢复，在所述至少一个中间恢复节点处恢复所述源时钟以产生恢复的中间时钟信号，从所述恢复的中间时钟信号新的时间戳分组基于所述恢复的中间时钟信号传送定时信息，并将所述新的时间戳分组转发到所述目的地节点。

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