专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120273889A1 SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER 有权
标题翻译：用于SOI结构的小型隔离分离器
公开(公告)号：US20120273889A1
公开(公告)日：2012-11-01
申请号：US13548304
申请日：2012-07-13
申请人： Konstantin V. LOIKO , Toni D. VAN GOMPEL , Rode R. MORA , Michael D. TURNER , Brian A. WINSTEAD , Mark D. HALL
发明人： Konstantin V. LOIKO , Toni D. VAN GOMPEL , Rode R. MORA , Michael D. TURNER , Brian A. WINSTEAD , Mark D. HALL
IPC分类号： H01L29/772
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/66477 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210）其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

2. 发明授权

US08766362B2 Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner 有权
标题翻译：浅沟槽隔离用于结合侧墙和底衬的SOI结构
公开(公告)号：US08766362B2
公开(公告)日：2014-07-01
申请号：US13548304
申请日：2012-07-13
申请人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
发明人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/66477 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210）其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

3. 发明授权

US07829447B2 Semiconductor structure pattern formation 有权
标题翻译：半导体结构图形形成
公开(公告)号：US07829447B2
公开(公告)日：2010-11-09
申请号：US11419304
申请日：2006-05-19
申请人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
发明人： Leo Mathew , Rode R. Mora , Tab A. Stephens , Tien Ying Luo
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/785 , H01L29/66795 , Y10S438/942
摘要： Forming structures such as fins in a semiconductor layer according to a pattern formed by oxidizing a sidewall of a layer of oxidizable material. In one embodiment, source/drain pattern structures and a fin pattern structures are patterned in the oxidizable layer. The fin pattern structure is then masked from an oxidation process that grows oxide on the sidewalls of the channel pattern structure and the top surface of the source/drain pattern structures. The remaining oxidizable material of the channel pattern structure is subsequently removed leaving a hole between two portions of the oxide layer. These two portions are used in one embodiment as a mask for patterning the semiconductor layer to form two fins. This patterning also leaves the source/drain structures connected to the fins.
摘要翻译：根据通过氧化可氧化材料层的侧壁形成的图案在半导体层中形成诸如翅片的结构。在一个实施例中，在可氧化层中图案化源极/漏极图案结构和鳍状图案结构。然后从在沟道图案结构的侧壁和源极/漏极图案结构的顶表面上生长氧化物的氧化过程掩蔽鳍状图案结构。随后去除沟道图案结构的剩余可氧化材料，留下氧化物层的两个部分之间的孔。这两个部分在一个实施例中用作用于图案化半导体层以形成两个散热片的掩模。该图案化还使得源极/漏极结构连接到鳍片。

4. 发明授权

US06951783B2 Confined spacers for double gate transistor semiconductor fabrication process 有权
标题翻译：用于双栅晶体管半导体制造工艺的密封间隔物
公开(公告)号：US06951783B2
公开(公告)日：2005-10-04
申请号：US10695163
申请日：2003-10-28
申请人： Leo Mathew , Rode R. Mora , Bich-Yen Nguyen , Tab A. Stephens , Anne M. Vandooren
发明人： Leo Mathew , Rode R. Mora , Bich-Yen Nguyen , Tab A. Stephens , Anne M. Vandooren
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/84
CPC分类号： H01L29/785 , H01L21/823437 , H01L21/823468 , H01L29/66628 , H01L29/66795 , H01L29/66818
摘要： A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.
摘要翻译：半导体制造工艺包括形成覆盖衬底的硅片。栅极电介质形成在鳍片的主面上。在鳍片的至少两个面上形成栅电极。然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。此后，在主翅片面上形成硅化物。在一个实施例中，栅极电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

5. 发明申请

US20140299935A1 SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER 审中-公开
标题翻译：用于SOI结构的小型隔离分离器
公开(公告)号：US20140299935A1
公开(公告)日：2014-10-09
申请号：US14308816
申请日：2014-06-19
申请人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
发明人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
IPC分类号： H01L27/12 , H01L29/78 , H01L29/161 , H01L29/06 , H01L29/16 , H01L29/66
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/66477 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210）其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

6. 发明授权

US07998822B2 Semiconductor fabrication process including silicide stringer removal processing 有权
标题翻译：半导体制造工艺包括硅化物棱镜去除处理
公开(公告)号：US07998822B2
公开(公告)日：2011-08-16
申请号：US12244413
申请日：2008-10-02
申请人： Dharmesh Jawarani , John R. Alvis , Michael G. Harrison , Leo Mathew , John E. Moore , Rode R. Mora
发明人： Dharmesh Jawarani , John R. Alvis , Michael G. Harrison , Leo Mathew , John E. Moore , Rode R. Mora
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , H01L21/2855
摘要： A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134). After the etch back the wafer (101) may be dipped in piranha solution and cleaned with an RF sputter (140) of argon.
摘要翻译：半导体制造工艺包括形成覆盖在晶片（101）的半导体衬底（104）上的栅极电介质（114）上的栅电极（112）和包括垂直部分（118）的衬垫电介质层（116）栅电极和覆盖在半导体衬底（104）的上表面上的水平部分（117）。邻近垂直部分（118）并且覆盖衬里介电层（116）的水平部分（117）形成间隔物（108）。在形成间隔物（108）之后，去除衬里电介质层（116）的暴露部分以形成被延伸间隔物（108）覆盖的衬里电介质结构（126）。然后将延伸垫片（108）回蚀刻以露出或揭开衬垫介质结构（126）的四肢。在蚀刻回间隔物（108）之前，金属（130）可以溅射沉积在晶片（101）上，准备形成硅化物（134）。在蚀刻之后，晶片（101）可以浸入食人鱼溶液中并用氩气的RF溅射（140）清洁。

7. 发明授权

US07579243B2 Split gate memory cell method 有权
标题翻译：分闸存储单元法
公开(公告)号：US07579243B2
公开(公告)日：2009-08-25
申请号：US11535345
申请日：2006-09-26
申请人： Sung-Taeg Kang , Rode R. Mora , Robert F. Steimle
发明人： Sung-Taeg Kang , Rode R. Mora , Robert F. Steimle
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/28132 , B82Y10/00 , H01L21/28273 , H01L21/823425 , H01L21/823468 , H01L29/66484 , H01L29/665 , H01L29/66825 , H01L29/7831 , H01L29/7833 , H01L29/7881
摘要： Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.
摘要翻译：分离栅极存储单元形成包括在衬底上形成牺牲层。牺牲层被图案化以形成具有第一侧壁和第二侧壁的牺牲结构。在衬底上形成一层纳米晶体。在衬底上沉积第一层多晶硅。在第一多晶硅层上的各向异性蚀刻形成邻近第一侧壁的第一多晶硅侧壁间隔物和邻近第二侧壁的第二多晶硅侧壁间隔物。去除牺牲结构离开第一侧壁间隔物和第二侧壁间隔物。第二层多晶硅沉积在第一和第二侧壁间隔物和基底上。在第二多晶硅层上的各向异性蚀刻形成与第一侧壁间隔物的第一侧相邻的第三侧壁间隔物和邻近第二侧壁间隔物的第一侧的第四侧壁间隔物。

8. 发明申请

US20080076221A1 SPLIT GATE MEMORY CELL METHOD 有权
标题翻译：分离栅存储单元方法
公开(公告)号：US20080076221A1
公开(公告)日：2008-03-27
申请号：US11535345
申请日：2006-09-26
申请人： Sung-Taeg Kang , Rode R. Mora , Robert F. Steimle
发明人： Sung-Taeg Kang , Rode R. Mora , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , B82Y10/00 , H01L21/28273 , H01L21/823425 , H01L21/823468 , H01L29/66484 , H01L29/665 , H01L29/66825 , H01L29/7831 , H01L29/7833 , H01L29/7881
摘要： Split gate memory cell formation includes forming a sacrificial layer over a substrate. The sacrificial layer is patterned to form a sacrificial structure with a first sidewall and a second sidewall. A layer of nanocrystals is formed over the substrate. A first layer of polysilicon is deposited over the substrate. An anisotropic etch on the first polysilicon layer forms a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall. Removal of the sacrificial structure leaves the first sidewall spacer and the second sidewall spacer. A second layer of polysilicon is deposited over the first and second sidewall spacers and the substrate. An anisotropic etch on the second layer of polysilicon forms a third sidewall spacer adjacent to a first side of the first sidewall spacer and a fourth sidewall spacer adjacent to a first side of the second sidewall spacer.
摘要翻译：分离栅极存储单元形成包括在衬底上形成牺牲层。牺牲层被图案化以形成具有第一侧壁和第二侧壁的牺牲结构。在衬底上形成一层纳米晶体。在衬底上沉积第一层多晶硅。在第一多晶硅层上的各向异性蚀刻形成邻近第一侧壁的第一多晶硅侧壁间隔物和邻近第二侧壁的第二多晶硅侧壁间隔物。去除牺牲结构离开第一侧壁间隔物和第二侧壁间隔物。第二层多晶硅沉积在第一和第二侧壁间隔物和基底上。在第二多晶硅层上的各向异性蚀刻形成与第一侧壁间隔物的第一侧相邻的第三侧壁间隔物和邻近第二侧壁间隔物的第一侧的第四侧壁间隔物。

9. 发明授权

US08513066B2 Method of making an inverted-T channel transistor 有权
标题翻译：制造倒T沟道晶体管的方法
公开(公告)号：US08513066B2
公开(公告)日：2013-08-20
申请号：US11257973
申请日：2005-10-25
申请人： Leo Mathew , Rode R. Mora
发明人： Leo Mathew , Rode R. Mora
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/1104 , H01L21/823431 , H01L27/11 , H01L29/66795 , H01L29/785
摘要： A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region. The method further includes removing a portion of the horizontal active region, which is not covered by the sidewall spacer. The method further includes removing the sidewall spacer. The method further includes forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region. The method further includes forming a gate electrode over the gate dielectric. The method further includes forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.
摘要翻译：提供了一种用于产生逆T场效应晶体管的方法。该方法包括在衬底上创建水平有源区和垂直有源区。该方法还包括在垂直有源区的第一侧和垂直有源区的第二侧上形成侧壁间隔物。该方法还包括移除未被侧壁间隔物覆盖的水平有源区的一部分。该方法还包括去除侧壁间隔物。该方法还包括在水平有源区域的至少第一部分和垂直有源区域的至少第一部分上形成栅极电介质。该方法还包括在栅极电介质上形成栅电极。该方法还包括在水平有源区域的至少第二部分和垂直有源区域的至少第二部分上形成源极区域和漏极区域。

10. 发明授权

US07528078B2 Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer 有权
标题翻译：形成电子器件的工艺包括与半导体层内的开口相邻的致密的氮化物层
公开(公告)号：US07528078B2
公开(公告)日：2009-05-05
申请号：US11433298
申请日：2006-05-12
申请人： Toni D. Van Gompel , Kuang-Hsin Chen , Laegu Kang , Rode R. Mora , Michael D. Turner
发明人： Toni D. Van Gompel , Kuang-Hsin Chen , Laegu Kang , Rode R. Mora , Michael D. Turner
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31111 , H01L21/3105 , H01L21/31116 , H01L21/76205
摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.
摘要翻译：形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。在图案化半导体层之后，开口可以具有底部，并且半导体层可以具有侧壁和表面。表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。该方法还可以包括在开口内沉积氮化物层，其中使用PECVD技术进行沉积。该方法还可以包括使氮化物层致密化。该方法还可以进一步包括去除氮化物层的一部分，其中氮化物层的剩余部分可以位于开口内并且与表面间隔开。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式