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1. 发明授权

US08637984B2 Multi-chip package with pillar connection 失效
标题翻译：多芯片封装，支柱连接
公开(公告)号：US08637984B2
公开(公告)日：2014-01-28
申请号：US13088817
申请日：2011-04-18
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： H01L23/48 , H01L21/58
CPC分类号： H01L25/50 , H01L21/4853 , H01L23/49811 , H01L24/05 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/16105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73265 , H01L2224/8114 , H01L2224/81192 , H01L2224/81193 , H01L2224/81194 , H01L2224/92127 , H01L2225/0651 , H01L2225/06517 , H01L2225/06551 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a substrate having a first plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice is disposed on the substrate. Each die of the plurality of dice has a first plurality of die bonding pads arranged along at least one first edge thereof. A plurality of bonding pillars extends substantially vertically from the substrate bonding pads. Each bonding pillar electrically connects one of the first plurality of substrate bonding pads to a corresponding one of the first plurality of die bonding pads. A method of assembling a semiconductor device is also described.
摘要翻译：半导体器件具有基板，该基板具有设置在其接合表面上的第一多个基板接合焊盘。多个半导体管芯设置在基板上。多个骰子中的每个管芯具有沿其至少一个第一边缘布置的第一多个管芯接合焊盘。多个接合柱从衬底接合焊盘基本垂直地延伸。每个接合柱将第一多个基板接合焊盘中的一个电连接到第一多个管芯接合焊盘中的对应的一个。还描述了组装半导体器件的方法。

2. 发明授权

US08604593B2 Reconfiguring through silicon vias in stacked multi-die packages 有权
公开(公告)号：US08604593B2
公开(公告)日：2013-12-10
申请号：US12773340
申请日：2010-05-04
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , G11C29/808 , H01L23/481 , H01L25/18 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.

3. 发明申请

US20120001314A1 MULTI-CHIP PACKAGE WITH THERMAL FRAME AND METHOD OF ASSEMBLING 有权
标题翻译：具有热框架的多芯片包装和组装方法
公开(公告)号：US20120001314A1
公开(公告)日：2012-01-05
申请号：US13090427
申请日：2011-04-20
申请人： Roland SCHUETZ
发明人： Roland SCHUETZ
IPC分类号： H01L23/34
CPC分类号： H01L23/367 , H01L24/48 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2225/06589 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a substrate having a plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice are stacked on the bonding surface of the substrate to form a die stack. Each die has a plurality of die bonding pads arranged along at least one bonding edge thereof. The remaining edges of each die are non-bonding edges. A plurality of bonding wires each electrically connects one of the die bonding pads to one of the substrate bonding pads. At least one thermally conductive layer is disposed between two adjacent semiconductor dice. At least one thermally conductive lateral portion is in thermal contact with the at least one layer of thermally conductive material. Each thermally conductive lateral portion is arranged along a non-bonding edge of the die stack.
摘要翻译：半导体器件包括具有设置在其接合表面上的多个衬底接合焊盘的衬底。多个半导体管芯堆叠在基板的接合表面上以形成管芯堆叠。每个管芯具有沿其至少一个接合边缘布置的多个管芯接合焊盘。每个模具的剩余边缘是非粘合边缘。多个接合线将芯片接合焊盘之一电连接到衬底接合焊盘之一。至少一个导热层设置在两个相邻的半导体管芯之间。至少一个导热侧向部分与所述至少一个导热材料层热接触。每个导热侧面部分沿着芯片堆叠的非粘结边缘布置。

4. 发明申请

US20110096614A1 SINGLE-STROBE OPERATION OF MEMORY DEVICES 有权
标题翻译：存储器件的单行程操作
公开(公告)号：US20110096614A1
公开(公告)日：2011-04-28
申请号：US12984987
申请日：2011-01-05
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

5. 发明申请

US20110090004A1 RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES 有权
标题翻译：通过堆叠的多层包装中的硅胶重新构造
公开(公告)号：US20110090004A1
公开(公告)日：2011-04-21
申请号：US12773340
申请日：2010-05-04
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： H01L25/00 , H01L23/538 , H01L25/065
CPC分类号： H01L25/0657 , G11C29/808 , H01L23/481 , H01L25/18 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.
摘要翻译：通过堆叠多芯片集成电路封装中的硅通孔（TSV）被控制为在其正常任务模式下在封装的现场操作期间根据需要采取不同的连接配置。可以重新配置TSV连接以以不同于例如该管芯的工厂默认连接的方式连接受影响的管芯。可以改变与管芯本机电路的输入和/或输出的TSV连接。芯片可以从互连堆叠中的裸片的接口完全断开，或者原本与此接口断开连接的裸片可能连接到接口。

6. 发明申请

US20090103378A1 SINGLE-STROBE OPERATION OF MEMORY DEVICES 有权
标题翻译：存储器件的单行程操作
公开(公告)号：US20090103378A1
公开(公告)日：2009-04-23
申请号：US11873475
申请日：2007-10-17
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

7. 发明授权

US08443233B2 Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices 有权
标题翻译：串联连接半导体器件配置中故障隔离和数据恢复的方法和系统
公开(公告)号：US08443233B2
公开(公告)日：2013-05-14
申请号：US12945280
申请日：2010-11-12
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G11C29/1201 , G11C29/32 , G11C29/44 , G11C29/86 , G11C2029/0409
摘要： A method of identifying at least one anomalous device in a configuration of series-connected semiconductor devices, comprising: selecting a device in the configuration; sending a command to the selected device, the command for placing the selected device into a recovery mode of operation; attempting to elicit identification data from the selected device while in the recovery mode of operation; if the attempt is successful, selecting a next device in the configuration of series-connected semiconductor devices and repeating the sending and the attempting to elicit; and if the attempt is unsuccessful, concluding that the selected device is an anomalous device. Also, a method of recovering data from a configuration of series-connected semiconductor memory devices having undergone a failure, comprising: placing an operable device of the configuration into a recovery mode of operation; while the operable device is in the recovery mode of operation, retrieving data currently stored by the operable device; and storing the retrieved data in an alternate memory facility.
摘要翻译：一种在串联连接的半导体器件的配置中识别至少一个异常器件的方法，包括：选择所述配置中的器件; 向所选设备发送命令，将所选择的设备置于恢复操作模式的命令; 在恢复操作模式下尝试从所选设备中引出识别数据; 如果尝试成功，则选择串联连接的半导体器件的配置中的下一个器件，并重复发送和尝试引出; 并且如果尝试不成功，则认为所选择的设备是异常设备。另外，从已经发生故障的串联连接的半导体存储器件的配置中恢复数据的方法包括：将配置的可操作装置放置在恢复操作模式中; 而可操作设备处于恢复操作模式，检索由可操作设备当前存储的数据; 以及将检索的数据存储在备用存储器设备中。

8. 发明申请

US20110276775A1 METHOD AND APPARATUS FOR CONCURRENTLY READING A PLURALITY OF MEMORY DEVICES USING A SINGLE BUFFER 审中-公开
标题翻译：使用单个缓冲器来同时读取大量存储器件的方法和装置
公开(公告)号：US20110276775A1
公开(公告)日：2011-11-10
申请号：US13102310
申请日：2011-05-06
申请人： Roland SCHUETZ
发明人： Roland SCHUETZ
IPC分类号： G06F12/02
CPC分类号： G06F13/1673
摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.
摘要翻译：一种复合存储器件，包括分立存储器件和用于响应具有与存储器件不兼容的格式或协议的全局存储器控制信号来控制分立存储器件的桥接器件。分立存储器件可以是对现有或本地存储器控制信号进行响应的商业现成存储器件或定制存储器件。全局和本地存储器控制信号包括各自具有不同格式的命令和命令信号。复合存储器件包括包括分立存储器件和桥接器件的半导体管芯的封装的系统，或者可以包括具有封装的分立存储器件的印刷电路板和安装在其上的封装桥接器件。

9. 发明申请

US20110060937A1 METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES 有权
标题翻译：串联连接半导体器件配置中的故障隔离和数据恢复的方法和系统
公开(公告)号：US20110060937A1
公开(公告)日：2011-03-10
申请号：US12945280
申请日：2010-11-12
申请人： Roland SCHUETZ
发明人： Roland SCHUETZ
IPC分类号： G06F11/07
CPC分类号： G06F11/004 , G11C29/1201 , G11C29/32 , G11C29/44 , G11C29/86 , G11C2029/0409
摘要： A method of identifying at least one anomalous device in a configuration of series-connected semiconductor devices, comprising: selecting a device in the configuration; sending a command to the selected device, the command for placing the selected device into a recovery mode of operation; attempting to elicit identification data from the selected device while in the recovery mode of operation; if the attempt is successful, selecting a next device in the configuration of series-connected semiconductor devices and repeating the sending and the attempting to elicit; and if the attempt is unsuccessful, concluding that the selected device is an anomalous device. Also, a method of recovering data from a configuration of series-connected semiconductor memory devices having undergone a failure, comprising: placing an operable device of the configuration into a recovery mode of operation; while the operable device is in the recovery mode of operation, retrieving data currently stored by the operable device; and storing the retrieved data in an alternate memory facility.
摘要翻译：一种在串联连接的半导体器件的配置中识别至少一个异常器件的方法，包括：选择所述配置中的器件; 向所选设备发送命令，将所选择的设备置于恢复操作模式的命令; 在恢复操作模式下尝试从所选设备中引出识别数据; 如果尝试成功，则选择串联连接的半导体器件的配置中的下一个器件，并重复发送和尝试引出; 并且如果尝试不成功，则认为所选择的设备是异常设备。另外，从已经发生故障的串联连接的半导体存储器件的配置中恢复数据的方法包括：将配置的可操作装置放置在恢复操作模式中; 而可操作设备处于恢复操作模式，检索由可操作设备当前存储的数据; 以及将检索的数据存储在备用存储器设备中。

10. 发明授权

US07889578B2 Single-strobe operation of memory devices 有权
标题翻译：存储器件的单次选通操作
公开(公告)号：US07889578B2
公开(公告)日：2011-02-15
申请号：US11873475
申请日：2007-10-17
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

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