专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110096614A1 SINGLE-STROBE OPERATION OF MEMORY DEVICES 有权
标题翻译：存储器件的单行程操作
公开(公告)号：US20110096614A1
公开(公告)日：2011-04-28
申请号：US12984987
申请日：2011-01-05
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

2. 发明申请

US20090103378A1 SINGLE-STROBE OPERATION OF MEMORY DEVICES 有权
标题翻译：存储器件的单行程操作
公开(公告)号：US20090103378A1
公开(公告)日：2009-04-23
申请号：US11873475
申请日：2007-10-17
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

3. 发明授权

US08406070B2 Single-strobe operation of memory devices 有权
标题翻译：存储器件的单次选通操作
公开(公告)号：US08406070B2
公开(公告)日：2013-03-26
申请号：US12984987
申请日：2011-01-05
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

4. 发明授权

US07889578B2 Single-strobe operation of memory devices 有权
标题翻译：存储器件的单次选通操作
公开(公告)号：US07889578B2
公开(公告)日：2011-02-15
申请号：US11873475
申请日：2007-10-17
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

5. 发明授权

US09588883B2 Flash memory system 有权
标题翻译：闪存系统
公开(公告)号：US09588883B2
公开(公告)日：2017-03-07
申请号：US13455780
申请日：2012-04-25
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G06F12/02
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0679 , G06F12/0246 , G06F2212/7201
摘要： A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.
摘要翻译：一种用于控制MBC配置的闪存设备以在SBC存储模式或部分MBC存储模式下存储数据的方法和系统。在完整的MBC存储模式中，对于存储器单元的每个物理行，从第一页到第N页顺序编程数据页。每行存储器单元最多有N个虚拟页面地址，每个页面被编程用于指定行中的页面的虚拟位置。对于SBC或部分MBC数据存储，闪存控制器使用少于每行的最大N个虚拟页面地址向MBC存储器件发出程序命令。 MBC存储器件顺序地执行到行的最后接收的虚拟页地址的编程操作。

6. 发明授权

US08854884B2 NAND flash architecture with multi-level row decoding 有权
标题翻译： NAND Flash架构采用多级行解码
公开(公告)号：US08854884B2
公开(公告)日：2014-10-07
申请号：US13467491
申请日：2012-05-09
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C16/04 , G11C16/16 , G11C8/10 , G11C16/10 , G11C8/12 , G11C16/08 , G11C8/14 , G11C11/56
CPC分类号： G11C8/14 , G11C8/10 , G11C8/12 , G11C11/5621 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C2211/5642
摘要： A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.
摘要翻译：公开了一种NAND闪速存储器件。 NAND闪存器件包括被定义为多个扇区的NAND快闪存储器阵列。行解码在两个级别执行。执行适用于所有部门的第一级。例如，这可以用于选择块。例如，针对特定扇区执行第二级别，以选择特定扇区中的块内的页面。对扇区内的页面的分辨率进行读取和编程操作，同时对扇区内的块的分辨率进行擦除操作。

7. 发明授权

US08797799B2 Device selection schemes in multi chip package NAND flash memory system 有权
标题翻译：多芯片封装NAND闪存系统中的器件选择方案
公开(公告)号：US08797799B2
公开(公告)日：2014-08-05
申请号：US13611580
申请日：2012-09-12
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C15/00 , G11C16/04 , G11C16/26 , G11C15/04
CPC分类号： G11C15/046 , G11C7/109 , G11C8/12 , G11C16/0483 , G11C16/06 , G11C16/08
摘要： Systems and methods are provided for perform device selection in multi-chip package NAND flash memory systems. In some embodiments, the memory controller performs device selection by command. In other embodiments, the memory controller performs device selection by input address.
摘要翻译：提供了用于在多芯片封装NAND闪存系统中执行设备选择的系统和方法。在一些实施例中，存储器控制器通过命令执行设备选择。在其他实施例中，存储器控制器通过输入地址执行设备选择。

8. 发明授权

US08724382B2 Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same 有权
标题翻译：具有极性控制的多单元（MBC）非易失性存储装置和系统的编程方法相同
公开(公告)号：US08724382B2
公开(公告)日：2014-05-13
申请号：US13117715
申请日：2011-05-27
申请人： Jin-Ki Kim , William Francis Petrie
发明人： Jin-Ki Kim , William Francis Petrie
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C29/00 , G11C2211/5646 , G11C2211/5647
摘要： A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.
摘要翻译：一种多比特单元（MBC）非易失性存储装置，方法和系统，其中用于向/从存储器阵列写入/读取数据的控制器通过选择性地反转数据字来控制数据的极性，以最大化位数（M-1）个虚拟页面内编程，并选择性地反转数据字以最小化要在第M个虚拟页面中编程的位数，其中M是每个单元的位数。当数据字反转时，设置相应的极性控制标志。当从M个虚拟页面读取时，根据相应的极性标志选择性地反转数据。许多最高阈值电压编程状态在减少。这提供了编程单元阈值电压的更严格的分配，降低的功耗，减少的编程时间和增强的器件可靠性。

9. 发明授权

US08619493B2 Flexible memory operations in NAND flash devices 有权
标题翻译： NAND闪存器件中灵活的存储器操作
公开(公告)号：US08619493B2
公开(公告)日：2013-12-31
申请号：US13348107
申请日：2012-01-11
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C7/10
CPC分类号： G11C16/08 , G06F12/0246 , G11C7/1045 , G11C8/08 , G11C8/10 , G11C16/0483 , G11C16/10 , G11C2216/22
摘要： A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase operations. Each core controller controls timing and activation of row circuits, column circuits, voltage generators, and local input/output path circuits for a corresponding memory access operation of the bank. Concurrent operations are executable in multiple banks to improve performance. Each bank has a page size that is configurable with page size configuration data such that only selected wordlines are activated in response to address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank.
摘要翻译：具有至少两个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小和核心控制器。核心控制器是每个银行本地的，并且管理银行的存储器访问操作，包括读取，编程和擦除操作。每个核心控制器控制行电路，列电路，电压发生器和本地输入/输出路径电路的定时和激活，用于存储体的相应存储器存取操作。并发操作可在多个银行中执行，以提高性能。每个银行的页面大小可配置页面大小的配置数据，以便仅响应于地址数据激活所选择的字线。在上电时，可以将组态数据加载到存储器件中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。

10. 发明授权

US08533405B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08533405B2
公开(公告)日：2013-09-10
申请号：US12812500
申请日：2008-12-16
申请人： Jin-Ki Kim , Daniel Albert Hammond
发明人： Jin-Ki Kim , Daniel Albert Hammond
IPC分类号： G06F12/00 , G11C11/34 , G11C8/00
CPC分类号： G11C16/08 , G11C5/025 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/14 , G11C29/76 , H04L12/46
摘要： A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device.
摘要翻译：公开了具有两个存储容量的非功率的非易失性存储器。非易失性存储器件包括至少一个平面。平面包括多个块，其中每个块划分成多个页面，并且每个块沿着第一维由第一数量的存储单元定义用于存储数据，并且沿着第二维度由第二数量的第二维度用于存储数据的存储单元。非易失性存储器具有与所述平面中的存储单元的总数成比例地相关的两个容量的非功率。非易失性存储器还包括多个行解码器。在存储器装置中，至少基本上一对一的关系存在多个行解码器到页数。行解码器中的每一个被配置为便于在存储器件的相关页面上进行读取操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式