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1. 发明授权

US07889578B2 Single-strobe operation of memory devices 有权
标题翻译：存储器件的单次选通操作
公开(公告)号：US07889578B2
公开(公告)日：2011-02-15
申请号：US11873475
申请日：2007-10-17
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

2. 发明授权

US08406070B2 Single-strobe operation of memory devices 有权
标题翻译：存储器件的单次选通操作
公开(公告)号：US08406070B2
公开(公告)日：2013-03-26
申请号：US12984987
申请日：2011-01-05
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

3. 发明申请

US20110096614A1 SINGLE-STROBE OPERATION OF MEMORY DEVICES 有权
标题翻译：存储器件的单行程操作
公开(公告)号：US20110096614A1
公开(公告)日：2011-04-28
申请号：US12984987
申请日：2011-01-05
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

4. 发明申请

US20090103378A1 SINGLE-STROBE OPERATION OF MEMORY DEVICES 有权
标题翻译：存储器件的单行程操作
公开(公告)号：US20090103378A1
公开(公告)日：2009-04-23
申请号：US11873475
申请日：2007-10-17
申请人： Roland Schuetz , Jin-Ki Kim
发明人： Roland Schuetz , Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093
摘要： An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.
摘要翻译：存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。便利减少引脚数接口，将多个选通信号降低到单个选通信号。此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

5. 发明授权

US08443233B2 Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices 有权
标题翻译：串联连接半导体器件配置中故障隔离和数据恢复的方法和系统
公开(公告)号：US08443233B2
公开(公告)日：2013-05-14
申请号：US12945280
申请日：2010-11-12
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G11C29/1201 , G11C29/32 , G11C29/44 , G11C29/86 , G11C2029/0409
摘要： A method of identifying at least one anomalous device in a configuration of series-connected semiconductor devices, comprising: selecting a device in the configuration; sending a command to the selected device, the command for placing the selected device into a recovery mode of operation; attempting to elicit identification data from the selected device while in the recovery mode of operation; if the attempt is successful, selecting a next device in the configuration of series-connected semiconductor devices and repeating the sending and the attempting to elicit; and if the attempt is unsuccessful, concluding that the selected device is an anomalous device. Also, a method of recovering data from a configuration of series-connected semiconductor memory devices having undergone a failure, comprising: placing an operable device of the configuration into a recovery mode of operation; while the operable device is in the recovery mode of operation, retrieving data currently stored by the operable device; and storing the retrieved data in an alternate memory facility.
摘要翻译：一种在串联连接的半导体器件的配置中识别至少一个异常器件的方法，包括：选择所述配置中的器件; 向所选设备发送命令，将所选择的设备置于恢复操作模式的命令; 在恢复操作模式下尝试从所选设备中引出识别数据; 如果尝试成功，则选择串联连接的半导体器件的配置中的下一个器件，并重复发送和尝试引出; 并且如果尝试不成功，则认为所选择的设备是异常设备。另外，从已经发生故障的串联连接的半导体存储器件的配置中恢复数据的方法包括：将配置的可操作装置放置在恢复操作模式中; 而可操作设备处于恢复操作模式，检索由可操作设备当前存储的数据; 以及将检索的数据存储在备用存储器设备中。

6. 发明授权

US07836340B2 Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices 有权
标题翻译：串联连接半导体器件配置中故障隔离和数据恢复的方法和系统
公开(公告)号：US07836340B2
公开(公告)日：2010-11-16
申请号：US11941131
申请日：2007-11-16
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： G06F11/00
CPC分类号： G06F11/004 , G11C29/1201 , G11C29/32 , G11C29/44 , G11C29/86 , G11C2029/0409
摘要： A method of identifying at least one anomalous device in a configuration of series-connected semiconductor devices, comprising: selecting a device in the configuration; sending a command to the selected device, the command for placing the selected device into a recovery mode of operation; attempting to elicit identification data from the selected device while in the recovery mode of operation; if the attempt is successful, selecting a next device in the configuration of series-connected semiconductor devices and repeating the sending and the attempting to elicit; and if the attempt is unsuccessful, concluding that the selected device is an anomalous device. Also, a method of recovering data from a configuration of series-connected semiconductor memory devices having undergone a failure, comprising: placing an operable device of the configuration into a recovery mode of operation; while the operable device is in the recovery mode of operation, retrieving data currently stored by the operable device; and storing the retrieved data in an alternate memory facility.
摘要翻译：一种在串联连接的半导体器件的配置中识别至少一个异常器件的方法，包括：选择所述配置中的器件; 向所选设备发送命令，将所选择的设备置于恢复操作模式的命令; 在恢复操作模式下尝试从所选设备中引出识别数据; 如果尝试成功，则选择串联连接的半导体器件的配置中的下一个器件，并重复发送和尝试引出; 并且如果尝试不成功，则认为所选择的设备是异常设备。另外，从已经发生故障的串联连接的半导体存储器件的配置中恢复数据的方法包括：将配置的可操作装置放置在恢复操作模式中; 而可操作设备处于恢复操作模式，检索由可操作设备当前存储的数据; 以及将检索的数据存储在备用存储器设备中。

7. 发明授权

US08503211B2 Configurable module and memory subsystem 有权
标题翻译：可配置模块和内存子系统
公开(公告)号：US08503211B2
公开(公告)日：2013-08-06
申请号：US12770376
申请日：2010-04-29
申请人： Peter Gillingham , Roland Schuetz
发明人： Peter Gillingham , Roland Schuetz
IPC分类号： G11C5/00 , G11C5/02 , G11C5/06 , G11C8/00
CPC分类号： G11C5/025 , G06F13/1684 , G06F13/4022 , G06F13/4243 , G11C16/04
摘要： A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.
摘要翻译：可配置存储器子系统包括具有电路板的存储器模块，该电路板具有安装在其上的第一和第二存储器容纳装置（MCD）对。每个MCD对具有与第二MCD通信的第一MCD。每个MCD都有一个输入端口，一个输出端口和一个与桥连通的存储器。响应于命令，桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器，或者将存储器分组的一部分从存储器传送到输出端口。环回装置从第一MCD对接收命令和数据包，并将命令和数据包发送到第二MCD对。

8. 发明申请

US20130094271A1 CONNECTION OF MULTIPLE SEMICONDUCTOR MEMORY DEVICES WITH CHIP ENABLE FUNCTION 审中-公开
标题翻译：多芯半导体存储器件与芯片启用功能的连接
公开(公告)号：US20130094271A1
公开(公告)日：2013-04-18
申请号：US13588195
申请日：2012-08-17
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G06F13/4234 , G06F13/4247 , G11C5/066 , G11C7/10 , G11C7/20 , G11C16/08 , G11C2216/30
摘要： A system comprising a plurality of memory devices coupled by a common bus to a controller has a single serially coupled enable signal per channel. Each memory device or chip comprises a serial enable input and enable output and a register for storing a device identifier, e.g., chip ID. The memory devices are serially coupled by a serial enable link, for assertion of a single enable signal to all devices. This parallel data and serial enable configuration provides reduced per-channel pin count, relative to conventional systems that require a unique enable signal for each device. In operation, commands on the common bus targeting an individual device are asserted by adding an address field comprising a device identifier to each command string, preferably in an initial identification cycle of the command. Methods are also disclosed for initializing the system, comprising assigning device identifiers and obtaining a device count, prior to normal operation.
摘要翻译：包括通过公共总线耦合到控制器的多个存储器件的系统具有每个通道的单个串联耦合使能信号。每个存储器件或芯片包括串行使能输入和使能输出以及用于存储器件标识符（例如芯片ID）的寄存器。存储器件通过串行使能链路串联耦合，用于断言所有器件的单个使能信号。相对于需要每个器件的唯一使能信号的传统系统，这种并行数据和串行使能配置提供减少的每通道引脚数。在操作中，通过将优选地在命令的初始识别周期中添加包括设备标识符的地址字段到每个命令串来断言公共总线上针对单个设备的命令被断言。还公开了用于初始化系统的方法，包括在正常操作之前分配设备标识符并获得设备计数。

9. 发明授权

US09009423B2 Serially connected memory having subdivided data interface 有权
标题翻译：具有细分数据接口的串联存储器
公开(公告)号：US09009423B2
公开(公告)日：2015-04-14
申请号：US13643317
申请日：2011-04-26
申请人： Roland Schuetz
发明人： Roland Schuetz
IPC分类号： G06F12/00 , G06F13/16 , G11C7/10 , G11C8/18
CPC分类号： G06F12/00 , G06F13/1684 , G11C7/10 , G11C7/1003 , G11C8/18
摘要： A memory system has a controller. A plurality of memory devices are serially interconnected with the controller via an n-bit data interface. The memory system is configurable in a first mode to communicate each read and write operation between the controller and the memory devices using all n bits of the data interface. The memory system is configurable in a second mode to concurrently: communicate data associated with a first operation between the controller and a first target memory device using only m bits of the data interface, where m is less than n; and communicate data associated with a second operation between the controller and a second target memory device using the remaining n-m bits of the data interface. A memory device, a memory controller, and a method are also described.
摘要翻译：存储器系统具有控制器。多个存储器件经由n位数据接口与控制器串联连接。存储器系统可以在第一模式下配置，以使用数据接口的所有n位在控制器和存储器件之间传送每个读和写操作。存储器系统可配置为第二模式，以同时进行：仅使用数据接口的m位，传送与控制器和第一目标存储器件之间的第一操作相关联的数据，其中m小于n; 并且使用数据接口的剩余n-m位传送与控制器和第二目标存储设备之间的第二操作相关联的数据。还描述了存储器件，存储器控制器和方法。

10. 发明申请

US20100296256A1 CONFIGURABLE MODULE AND MEMORY SUBSYSTEM 有权
标题翻译：可配置模块和存储器子系统
公开(公告)号：US20100296256A1
公开(公告)日：2010-11-25
申请号：US12770376
申请日：2010-04-29
申请人： Peter Gillingham , Roland Schuetz
发明人： Peter Gillingham , Roland Schuetz
IPC分类号： H05K7/00
CPC分类号： G11C5/025 , G06F13/1684 , G06F13/4022 , G06F13/4243 , G11C16/04
摘要： A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.
摘要翻译：可配置存储器子系统包括具有电路板的存储器模块，该电路板具有安装在其上的第一和第二存储器容纳装置（MCD）对。每个MCD对具有与第二MCD通信的第一MCD。每个MCD都有一个输入端口，一个输出端口和一个与桥连通的存储器。响应于命令，桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器，或者将存储器分组的一部分从存储器传送到输出端口。环回装置从第一MCD对接收命令和数据包，并将命令和数据包发送到第二MCD对。

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