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1. 发明申请

US20100250842A1 HYBRID REGION CAM FOR REGION PREFETCHER AND METHODS THEREOF 有权
标题翻译：用于区域预混合物的混合区域CAM及其方法
公开(公告)号：US20100250842A1
公开(公告)日：2010-09-30
申请号：US12410891
申请日：2009-03-25
申请人： Mahadev S. Deshpande , Ronny L. Arnold , Paul L. Rogers , Douglas R. Williams
发明人： Mahadev S. Deshpande , Ronny L. Arnold , Paul L. Rogers , Douglas R. Williams
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F12/0862 , G06F2212/6026 , Y02D10/13
摘要： A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range.
摘要翻译：接收到第一个地址，并用于确定第一个地址范围。第一地址范围包括第二地址范围和第三地址范围。如果第一个地址在第二个地址范围内，则确定第四个地址范围。第四个地址范围与第一个地址范围不同。响应于确定第二地址处于第一地址范围或第四地址范围，从存储器检索信息。如果第一个地址在第三个地址范围内，则确定第五个地址范围。第五个地址范围与第一个地址范围不同。响应于确定第二地址处于第一地址范围或第五地址范围，从存储器检索其他信息。

2. 发明授权

US06745363B2 Early error detection using ECC 失效
标题翻译：使用ECC的早期错误检测
公开(公告)号：US06745363B2
公开(公告)日：2004-06-01
申请号：US10079451
申请日：2002-02-19
申请人： Christopher A. Poirier , Ronny L. Arnold
发明人： Christopher A. Poirier , Ronny L. Arnold
IPC分类号： G06F1110
CPC分类号： H03M13/6575 , H03M13/09 , H03M13/15
摘要： A method of rapidly detecting data errors includes generating a reference syndrome from data bits in a data word, the reference syndrome having at least a first portion and a second portion, generating a partial error code from the data bits and the first portion of the reference syndrome, and initiating an error recovery procedure if the partial error code contains any true values.
摘要翻译：一种快速检测数据错误的方法包括从数据字中的数据位产生参考校正子，参考校正子具有至少第一部分和第二部分，从数据位和参考的第一部分生成部分错误代码并且如果部分错误代码包含任何真实值，则启动错误恢复过程。

3. 发明申请

US20100262750A1 REGION PREFETCHER AND METHODS THEREOF 有权
标题翻译：地区预选者及其方法
公开(公告)号：US20100262750A1
公开(公告)日：2010-10-14
申请号：US12422467
申请日：2009-04-13
申请人： Mahadev S. Deshpande , Ronny L. Arnold , Josef A. Dvorak , Paul L. Rogers
发明人： Mahadev S. Deshpande , Ronny L. Arnold , Josef A. Dvorak , Paul L. Rogers
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.
摘要翻译：公开了一种预取设备和方法，该预取设备和方法基于从先前的高速缓存未命中地址收集的信息确定哪些地址推测性地取出数据。一个历史记录表明在存储器区域内与先前的高速缓存未命中地址的特定地址偏移处遇到高速缓存丢失的倾向，提供了未来指令所需的数据的增加可能性位于与当前缓存未命中地址。本文公开的预取设备维护导致高速缓存未命中的最近的六十四个唯一数据操作指令的高速缓存未命中地址和后续高速缓存未命中地址之间的关系的记录。该记录包括加权置信度值，其指示在从特定高速缓存未命中地址的偏移选择中的每一个处先前发生多少个高速缓存未命中。

4. 发明授权

US08195889B2 Hybrid region CAM for region prefetcher and methods thereof 有权
标题翻译：用于区域预取器的混合区域CAM及其方法
公开(公告)号：US08195889B2
公开(公告)日：2012-06-05
申请号：US12410891
申请日：2009-03-25
申请人： Mahadev S. Deshpande , Ronny L. Arnold , Paul L. Rogers , Douglas R. Williams
发明人： Mahadev S. Deshpande , Ronny L. Arnold , Paul L. Rogers , Douglas R. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026 , Y02D10/13
摘要： A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range.
摘要翻译：接收到第一个地址，并用于确定第一个地址范围。第一地址范围包括第二地址范围和第三地址范围。如果第一个地址在第二个地址范围内，则确定第四个地址范围。第四个地址范围与第一个地址范围不同。响应于确定第二地址处于第一地址范围或第四地址范围，从存储器检索信息。如果第一个地址在第三个地址范围内，则确定第五个地址范围。第五个地址范围与第一个地址范围不同。响应于确定第二地址处于第一地址范围或第五地址范围，从存储器检索其他信息。

5. 发明授权

US5689659A Method and apparatus for bursting operand transfers during dynamic bus sizing 失效
标题翻译：用于在动态总线调整过程中突发操作数传输的方法和装置
公开(公告)号：US5689659A
公开(公告)日：1997-11-18
申请号：US550043
申请日：1995-10-30
申请人： Donald L. Tietjen , Frank C. Galloway , Juan Guillermo Revilla , Nancy G. Woodbridge , David M. Menard , Ronny L. Arnold
发明人： Donald L. Tietjen , Frank C. Galloway , Juan Guillermo Revilla , Nancy G. Woodbridge , David M. Menard , Ronny L. Arnold
IPC分类号： G06F13/28 , G06F13/40 , G06F13/00
CPC分类号： G06F13/28 , G06F13/4018
摘要： A data processing system (10) having a bus controller (5) that uses a communication bus (22) which adapts to various system resources (7) and is capable of burst transfers. In one embodiment, the processor core (2) and system resources (7) supply control signals supplying required parameters of the next transfer. The bus controller is capable of transferring operands and/or instructions in incremental bursts from these system resources. Each transfer data burst has an associated unique access address where successive bytes of data are associated with sequential addresses and the burst increment equals the data port size. The burst capability is dependent on the ability of system resource (7) to burst data and can be inhibited with a transfer burst inhibit signal. The length of the desired data is controlled by a sizing signal from the core (2) or from cache and the increment size is supplied by the resource (7).
摘要翻译：一种具有总线控制器（5）的数据处理系统（10），该总线控制器（5）使用适应各种系统资源（7）并且能够进行突发传输的通信总线（22）。在一个实施例中，处理器核心（2）和系统资源（7）提供提供下一个传输的所需参数的控制信号。总线控制器能够以这些系统资源的增量突发传送操作数和/或指令。每个传输数据脉冲串具有相关联的唯一访问地址，其中连续的数据字节与顺序地址相关联，并且突发增量等于数据端口大小。突发能力取决于系统资源（7）突发数据的能力，并且可以用传输突发禁止信号来禁止。所需数据的长度由来自核心（2）或高速缓存的大小调整信号控制，增量大小由资源（7）提供。

6. 发明授权

US08677049B2 Region prefetcher and methods thereof 有权
标题翻译：区域预取器及其方法
公开(公告)号：US08677049B2
公开(公告)日：2014-03-18
申请号：US12422467
申请日：2009-04-13
申请人： Mahadev S. Deshpande , Ronny L. Arnold , Josef A. Dvorak , Paul L. Rogers
发明人： Mahadev S. Deshpande , Ronny L. Arnold , Josef A. Dvorak , Paul L. Rogers
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.
摘要翻译：公开了一种预取设备和方法，该预取设备和方法基于从先前的高速缓存未命中地址收集的信息确定哪些地址推测性地取出数据。一个历史记录表明在存储器区域内与先前的高速缓存未命中地址的特定地址偏移处遇到高速缓存丢失的倾向，提供了未来指令所需的数据的增加可能性位于与当前缓存未命中地址。本文公开的预取设备维护导致高速缓存未命中的最近的六十四个唯一数据操作指令的高速缓存未命中地址和后续高速缓存未命中地址之间的关系的记录。该记录包括加权置信度值，其指示在从特定高速缓存未命中地址的偏移选择中的每一个处先前发生多少个高速缓存未命中。

7. 发明授权

US5649125A Method and apparatus for address extension across a multiplexed communication bus 失效
标题翻译：多路复用通信总线上的地址扩展方法和装置
公开(公告)号：US5649125A
公开(公告)日：1997-07-15
申请号：US550311
申请日：1995-10-30
申请人： Donald L. Tietjen , Frank C. Galloway , David M. Menard , Ronny L. Arnold , Nancy G. Woodbridge
发明人： Donald L. Tietjen , Frank C. Galloway , David M. Menard , Ronny L. Arnold , Nancy G. Woodbridge
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/4217
摘要： A data processing system (10) having a bus controller (5) and a multiplexed communication bus (22) and provides a portion of the valid address information during the data phase. In one embodiment, in response to an address extension control signal, the bus controller (5) allocates the communication bus (22) to provide the address extension on conductors not needed for data, reducing the need for address latch circuitry. In an alternate embodiment, the bus controller (5) provides burst transfers where the processor core (2) increments a portion of each address with each data in the burst. For such burst transfers, the length of the desired data is controlled by a sizing signal (42) from the core (2) or from cache and the increment size is supplied by the system resource (7).
摘要翻译：一种具有总线控制器（5）和多路通信总线（22）的数据处理系统（10），并且在数据阶段期间提供有效地址信息的一部分。在一个实施例中，响应于地址扩展控制信号，总线控制器（5）分配通信总线（22）以在数据不需要的导体上提供地址扩展，从而减少对地址锁存电路的需要。在替代实施例中，总线控制器（5）提供突发传输，其中处理器核心（2）用突发中的每个数据递增每个地址的一部分。对于这样的突发传送，期望数据的长度由来自核心（2）或高速缓存的尺寸信号（42）控制，并且增量大小由系统资源（7）提供。

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