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1. 发明申请

US20100262750A1 REGION PREFETCHER AND METHODS THEREOF 有权
标题翻译：地区预选者及其方法
公开(公告)号：US20100262750A1
公开(公告)日：2010-10-14
申请号：US12422467
申请日：2009-04-13
申请人： Mahadev S. Deshpande , Ronny L. Arnold , Josef A. Dvorak , Paul L. Rogers
发明人： Mahadev S. Deshpande , Ronny L. Arnold , Josef A. Dvorak , Paul L. Rogers
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.
摘要翻译：公开了一种预取设备和方法，该预取设备和方法基于从先前的高速缓存未命中地址收集的信息确定哪些地址推测性地取出数据。一个历史记录表明在存储器区域内与先前的高速缓存未命中地址的特定地址偏移处遇到高速缓存丢失的倾向，提供了未来指令所需的数据的增加可能性位于与当前缓存未命中地址。本文公开的预取设备维护导致高速缓存未命中的最近的六十四个唯一数据操作指令的高速缓存未命中地址和后续高速缓存未命中地址之间的关系的记录。该记录包括加权置信度值，其指示在从特定高速缓存未命中地址的偏移选择中的每一个处先前发生多少个高速缓存未命中。

2. 发明授权

US08677049B2 Region prefetcher and methods thereof 有权
标题翻译：区域预取器及其方法
公开(公告)号：US08677049B2
公开(公告)日：2014-03-18
申请号：US12422467
申请日：2009-04-13
申请人： Mahadev S. Deshpande , Ronny L. Arnold , Josef A. Dvorak , Paul L. Rogers
发明人： Mahadev S. Deshpande , Ronny L. Arnold , Josef A. Dvorak , Paul L. Rogers
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.
摘要翻译：公开了一种预取设备和方法，该预取设备和方法基于从先前的高速缓存未命中地址收集的信息确定哪些地址推测性地取出数据。一个历史记录表明在存储器区域内与先前的高速缓存未命中地址的特定地址偏移处遇到高速缓存丢失的倾向，提供了未来指令所需的数据的增加可能性位于与当前缓存未命中地址。本文公开的预取设备维护导致高速缓存未命中的最近的六十四个唯一数据操作指令的高速缓存未命中地址和后续高速缓存未命中地址之间的关系的记录。该记录包括加权置信度值，其指示在从特定高速缓存未命中地址的偏移选择中的每一个处先前发生多少个高速缓存未命中。

3. 发明申请

US20100250842A1 HYBRID REGION CAM FOR REGION PREFETCHER AND METHODS THEREOF 有权
标题翻译：用于区域预混合物的混合区域CAM及其方法
公开(公告)号：US20100250842A1
公开(公告)日：2010-09-30
申请号：US12410891
申请日：2009-03-25
申请人： Mahadev S. Deshpande , Ronny L. Arnold , Paul L. Rogers , Douglas R. Williams
发明人： Mahadev S. Deshpande , Ronny L. Arnold , Paul L. Rogers , Douglas R. Williams
IPC分类号： G06F12/00 , G06F12/06
CPC分类号： G06F12/0862 , G06F2212/6026 , Y02D10/13
摘要： A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range.
摘要翻译：接收到第一个地址，并用于确定第一个地址范围。第一地址范围包括第二地址范围和第三地址范围。如果第一个地址在第二个地址范围内，则确定第四个地址范围。第四个地址范围与第一个地址范围不同。响应于确定第二地址处于第一地址范围或第四地址范围，从存储器检索信息。如果第一个地址在第三个地址范围内，则确定第五个地址范围。第五个地址范围与第一个地址范围不同。响应于确定第二地址处于第一地址范围或第五地址范围，从存储器检索其他信息。

4. 发明授权

US08195889B2 Hybrid region CAM for region prefetcher and methods thereof 有权
标题翻译：用于区域预取器的混合区域CAM及其方法
公开(公告)号：US08195889B2
公开(公告)日：2012-06-05
申请号：US12410891
申请日：2009-03-25
申请人： Mahadev S. Deshpande , Ronny L. Arnold , Paul L. Rogers , Douglas R. Williams
发明人： Mahadev S. Deshpande , Ronny L. Arnold , Paul L. Rogers , Douglas R. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026 , Y02D10/13
摘要： A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range.
摘要翻译：接收到第一个地址，并用于确定第一个地址范围。第一地址范围包括第二地址范围和第三地址范围。如果第一个地址在第二个地址范围内，则确定第四个地址范围。第四个地址范围与第一个地址范围不同。响应于确定第二地址处于第一地址范围或第四地址范围，从存储器检索信息。如果第一个地址在第三个地址范围内，则确定第五个地址范围。第五个地址范围与第一个地址范围不同。响应于确定第二地址处于第一地址范围或第五地址范围，从存储器检索其他信息。

5. 发明授权

US06918021B2 System of and method for flow control within a tag pipeline 有权
标题翻译：标签管道内的流量控制系统和方法
公开(公告)号：US06918021B2
公开(公告)日：2005-07-12
申请号：US10118801
申请日：2002-04-09
申请人： Robert F. Krick , David Johnson , Paul L. Rogers
发明人： Robert F. Krick , David Johnson , Paul L. Rogers
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831
摘要： A controller comprising a pipeline including a plurality of connected sequential elements wherein a first sequential element is connected to one or more transaction sources; a flow control logic including at least one resource utilization value register; resource allocation logic responsive to a transaction valid signal and one or more adjustment inputs, and comparison logic having a threshold value and a transaction control signal output connected to the one or more transaction sources; pipeline control logic having an adjustment output connected to the resource allocation logic; and a resource control logic having an output connected to an adjustment input of the resource allocation logic.
摘要翻译：一种包括流水线的控制器，包括多个连接的顺序元件，其中第一顺序元件连接到一个或多个交易源; 包括至少一个资源利用值寄存器的流控制逻辑; 响应于交易有效信号和一个或多个调整输入的资源分配逻辑，以及具有连接到所述一个或多个交易来源的阈值和交易控制信号输出的比较逻辑; 流水线控制逻辑具有连接到资源分配逻辑的调整输出; 以及具有连接到所述资源分配逻辑的调整输入的输出的资源控制逻辑。

6. 发明授权

US5380212A Conductive elastomeric interface for a pin grid array 失效
标题翻译：针阵列导电弹性体界面
公开(公告)号：US5380212A
公开(公告)日：1995-01-10
申请号：US70002
申请日：1993-05-28
申请人： James G. Smeenge, Jr. , Paul L. Rogers
发明人： James G. Smeenge, Jr. , Paul L. Rogers
IPC分类号： H01R12/71 , H01R13/24 , H05K7/10 , H01R4/58
CPC分类号： H01R13/2414 , H01R12/714 , H05K7/1061
摘要： An electrical interface connects a conductive pins to a printed circuit board. The electrical interface includes an elastomer holder having a plurality of holes. Elastomer conductors are placed in the plurality of holes within the elastomer holder. The elastomer holder is then attached to the printed circuit board so that each elastomer conductor comes into contact with a conductive pad on the printed circuit board. The conductive pins are placed in electrical contact with the elastomer conductors, for example, through a conductive socket. In the preferred embodiment the elastomer holder is composed of printed circuit board material. Before the elastomer holder is connected to the printed circuit board, the elastomer conductors are held in the holes in the elastomer holder using a throw-away retainer.
摘要翻译：电接口将导电引脚连接到印刷电路板。电接口包括具有多个孔的弹性体保持器。弹性体导体被放置在弹性体保持器内的多个孔中。然后将弹性体保持器附接到印刷电路板，使得每个弹性体导体与印刷电路板上的导电焊盘接触。导电引脚例如通过导电插座与弹性体导体电接触。在优选实施例中，弹性体保持器由印刷电路板材料构成。在弹性体保持器连接到印刷电路板之前，弹性体导体使用抛弃保持器保持在弹性体保持器的孔中。

7. 发明授权

US07032077B2 Multiple cache coherency 失效
标题翻译：多重缓存一致性
公开(公告)号：US07032077B2
公开(公告)日：2006-04-18
申请号：US10327778
申请日：2002-12-23
申请人： Paul L. Rogers , Robert F. Krick , Vipul Gandhi
发明人： Paul L. Rogers , Robert F. Krick , Vipul Gandhi
IPC分类号： G06F12/12
CPC分类号： G06F12/0831 , G06F12/0859
摘要： A memory architecture with a multiple cache coherency includes at least one processor with a storage area in communication with a cache memory. A main bus transmits and receives data to and from the cache memory and the processor. A coherency control in communication with the cache memory and the processor is configured to determine an existence or location of data in the cache memory or the storage area in response to a data request from the main bus. The coherency control dispatches an existence or location result to the main bus.
摘要翻译：具有多个高速缓存一致性的存储器架构包括至少一个具有与高速缓冲存储器通信的存储区域的处理器。主总线向高速缓冲存储器和处理器发送和接收数据。与高速缓冲存储器和处理器通信的一致性控制被配置为响应于来自主总线的数据请求来确定高速缓冲存储器或存储区域中的数据的存在或位置。一致性控制将存在或位置结果发送到主总线。

8. 发明授权

US06240523B1 Method and apparatus for automatically determining the phase relationship between two clocks generated from the same source 有权
标题翻译：用于自动确定从同一源产生的两个时钟之间的相位关系的方法和装置
公开(公告)号：US06240523B1
公开(公告)日：2001-05-29
申请号：US09365055
申请日：1999-07-30
申请人： Paul L. Rogers
发明人： Paul L. Rogers
IPC分类号： G06F104
CPC分类号： G06F1/12
摘要： A method and apparatus automatically determines a phase-based relationship between two clocks generated from the same source. In accordance with the present invention, a clock generator provides a clock signal to a sending IC and a receiving IC. The sending IC transmits data to the receiving IC over a data bus, and provides a strobe signal that is delayed by ¼ of a cycle of the internal clock of the sending IC to validate data at the receiving IC. The phase relationship between the strobe signal and the internal clock of receiving IC is initially unknown. Within the receiving IC, the strobe signal is used to form four round robin clock signals that clock data into four flip flops using a round robin scheme. Each of the round robin flip flops has a valid read window, and pair of multiplexors route the outputs of the round robin flip flops to a pair of flip flops that are clocked using internal clocks of the receiving IC. A select signal in the clock domain of the receiving IC is provided to the pair of multiplexors. The select signal can have one of two possible orientations. A phase detection circuit compares the phase of the select signal in the clock domain of the receiving IC with one of the round robin clock signals in the clock domain of the sending IC. If the phase detection circuit determines that the phase of the select signal has the proper, then the phase detect circuit does not toggle the orientation of the select signal. However, if the phase detection circuit determines that the select signal has an incorrect orientation, then the select signal is delayed for ½ of a cycle of the select signal, thereby establishing the proper orientation of the select signal.
摘要翻译：一种方法和装置自动地确定从相同源产生的两个时钟之间的基于相位的关系。根据本发明，时钟发生器向发送IC和接收IC提供时钟信号。发送IC通过数据总线向接收IC发送数据，并提供延迟发送IC的内部时钟的周期的1/4的选通信号，以验证接收IC处的数据。选通信号和接收IC的内部时钟之间的相位关系最初是未知的。在接收IC中，选通信号用于形成四个循环时钟信号，其使用循环方案将数据时钟数据转换成四个触发器。每个循环触发器具有有效的读取窗口，并且一对多路复用器将循环触发器的输出路由到使用接收IC的内部时钟计时的一对触发器。接收IC的时钟域中的选择信号被提供给该对多路复用器。选择信号可以具有两种可能取向之一。相位检测电路将接收IC的时钟域中的选择信号的相位与发送IC的时钟域中的循环时钟信号之一进行比较。如果相位检测电路确定选择信号的相位是否合适，则相位检测电路不会切换选择信号的方向。然而，如果相位检测电路确定选择信号具有不正确的方向，则选择信号被延迟到选择信号的一个周期的1/2，从而建立选择信号的正确取向。

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