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1. 发明授权

US08156402B2 Memory device with error correction capability and efficient partial word write operation 有权
标题翻译：具有纠错能力和高效部分字写操作的存储器件
公开(公告)号：US08156402B2
公开(公告)日：2012-04-10
申请号：US11994740
申请日：2007-04-26
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00 , G11C7/00 , G06F13/00
CPC分类号： G11C29/52 , G06F11/1008
摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。存储器件被配置为执行至少部分字写入操作和读取操作，其中部分字写入操作包括读取阶段和写入阶段。部分字写入操作的写入阶段在存储器件的相同时钟周期中发生在与读取操作相同的时钟周期中，例如在部分字写入操作的写入相位与时钟周期内的存储器阵列的时间复用位线之间，读操作。因此，部分字写入操作对于包含或以其他方式利用存储器件的更高级系统出现，就好像该操作仅需要存储器件的单个时钟周期。

2. 发明申请

US20110022648A1 Secure Random Number Generator 有权
标题翻译：安全随机数生成器
公开(公告)号：US20110022648A1
公开(公告)日：2011-01-27
申请号：US12934510
申请日：2008-05-23
申请人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F11/1008 , G11C11/412 , G11C2029/0411
摘要： A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.
摘要翻译：随机数发生器电路包括具有多个存储元件的第一存储器。当由施加到第一存储器的电压源供电时，每个存储元件具有与之对应的初始状态。第一存储器用于产生包括指示存储元件的相应初始状态的多个位的第一信号。随机数发生器电路还包括耦合到第一存储器的纠错电路。误差校正电路可操作以接收第一信号并且校正第一信号中的至少一个位，其在连续施加电力到第一存储器从而产生第二信号时不重复。第二信号是在连续向第一存储器施加电力时可重复的随机数。

3. 发明申请

US20100229035A1 SYSTEMATIC ERROR CORRECTION FOR MULTI-LEVEL FLASH MEMORY 有权
标题翻译：多级闪存存储器的系统错误校正
公开(公告)号：US20100229035A1
公开(公告)日：2010-09-09
申请号：US12682162
申请日：2007-10-31
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F11/14
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuitry within the memory, and iii) subsequent adjustment within that circuitry to cause a correction of systematic error in the output signal of the multi-level flash memory.
摘要翻译：根据示例性实施例，多级闪速存储器在读取多级闪速存储器时使用系统误差的误差校正。误差校正包括i）检测每个系统误差，ii）将系统误差反馈给存储器内的电路，以及iii）该电路内随后的调整，以引起多电平闪速存储器的输出信号中的系统误差的校正。

4. 发明申请

US20100182859A1 Method and Apparatus for Testing a Memory Device 有权
标题翻译：用于测试存储器件的方法和装置
公开(公告)号：US20100182859A1
公开(公告)日：2010-07-22
申请号：US12443776
申请日：2007-10-29
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/50
CPC分类号： G11C8/08 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/1202
摘要： Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.
摘要翻译：提供了用于测试半导体存储器件的技术。存储器件包括多个存储器单元和连接到存储器单元的多个行线和列线，用于选择性地访问一个或多个存储器单元。该方法包括以下步骤：将至少一个对应于待测试的存储器单元中的给定一个行的行中的至少一个施加第一电压，选择第一电压以强调第一电压的至少一个性能特征存储器件，所述第一电压不同于施加到所述给定行之一行的第二电压，用于在所述存储器件的正常操作期间访问所述存储器单元中的至少一个; 根据规定的测试参数锻炼记忆装置; 以及识别存储器件是否在测试参数的规定余量内可操作。

5. 发明授权

US07742355B2 Dynamic random access memory with low-power refresh 有权
标题翻译：动态随机存取存储器，低功耗刷新
公开(公告)号：US07742355B2
公开(公告)日：2010-06-22
申请号：US11962035
申请日：2007-12-20
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/401 , G11C11/406 , G11C29/50016 , G11C2211/4061 , G11C2211/4067
摘要： A technique to reduce refresh power in a DRAM. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a refresh controller that generates a refresh address and controls the refresh of the memory cells addressed by the refresh address. A marker memory is used by the refresh controller to determine which of the memory cells requires refreshing at a rate faster than the refresh rate of the remaining memory cells. Testing the DRAM uses a method to determine which of the memory cells are to be refreshed at the faster rate and to store the results in the marker memory.
摘要翻译：降低DRAM中的刷新功率的技术。在一个实施例中，以第一速率刷新所有DRAM存储器单元，并且以大于第一速率的第二速率刷新存储器单元的子集。在另一实施例中，DRAM具有产生刷新地址并控制由刷新地址寻址的存储器单元的刷新的刷新控制器。刷新控制器使用标记存储器来确定哪个存储器单元需要以比剩余存储器单元的刷新率更快的速率刷新。测试DRAM使用一种方法来确定要以更快的速率刷新哪些存储器单元并将结果存储在标记存储器中。

6. 发明授权

US07551512B2 Dual-port memory 有权
标题翻译：双端口内存
公开(公告)号：US07551512B2
公开(公告)日：2009-06-23
申请号：US11830417
申请日：2007-07-30
申请人： Donald Albert Evans , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Donald Albert Evans , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C8/00
CPC分类号： G11C7/1075
摘要： A dual-port memory circuit includes a plurality of memory sub-blocks. Each of the memory sub-blocks includes a plurality of single-port memory cells, at least one row line, and at least one local bit line, the row line and the bit line being coupled to the memory cells for selectively accessing the memory cells. The memory circuit further includes at least one global bit line connected to the plurality of memory sub-blocks. The global bit line is time-multiplexed during a given memory cycle such that the global bit line propagates data associated with a first port in the memory circuit during a first portion of the memory cycle, and the global bit line propagates data associated with a second port in the memory circuit during a second portion of the memory cycle.
摘要翻译：双端口存储器电路包括多个存储器子块。每个存储器子块包括多个单端口存储器单元，至少一个行线和至少一个局部位线，行线和位线被耦合到存储器单元，以选择性地访问存储器单元。存储器电路还包括连接到多个存储器子块的至少一个全局位线。全局位线在给定存储器周期期间被时分多路复用，使得全局位线在存储器周期的第一部分期间传播与存储器电路中的第一端口相关联的数据，并且全局位线传播与第二在存储器循环的第二部分期间存储器电路中的端口。

7. 发明授权

US06537867B1 High speed low voltage semiconductor devices and method of fabrication 有权
标题翻译：高速低压半导体器件及其制造方法
公开(公告)号：US06537867B1
公开(公告)日：2003-03-25
申请号：US09630463
申请日：2000-08-02
申请人： Ronald L. Freyman , Isik C. Kizilyalli , Ross A. Kohler , Omkaram Nalamasu , Mark R. Pinto , Joseph R. Radosevich , Robert M. Vella , George P. Watson
发明人： Ronald L. Freyman , Isik C. Kizilyalli , Ross A. Kohler , Omkaram Nalamasu , Mark R. Pinto , Joseph R. Radosevich , Robert M. Vella , George P. Watson
IPC分类号： H01L21336
CPC分类号： H01L21/32139
摘要： A digit signal processor capable of operating at 100 MHZ with a 1.0 volt power supply. The digital signal processor is fabricated by application of strong phase-shift lithography to obtain a 0.12 &mgr;m gate dimension. A dual-mask process is utilized to improve resolution thereby producing high speed, low-voltage processors. A n+/p+ dual-Poly:Si module, and dopant penetration suppression techniques may be utilized.
摘要翻译：一个数字信号处理器能够以1.0伏的电源工作在100MHZ。数字信号处理器是通过应用强相移光刻技术制造的，以获得0.12μm的门尺寸。利用双掩模工艺来提高分辨率，从而产生高速，低电压处理器。可以使用n + / p +双Poly：Si模块和掺杂剂渗透抑制技术。

8. 发明授权

US08566377B2 Secure random number generator 有权
标题翻译：安全随机数发生器
公开(公告)号：US08566377B2
公开(公告)日：2013-10-22
申请号：US12934510
申请日：2008-05-23
申请人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F11/1008 , G11C11/412 , G11C2029/0411
摘要： A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.
摘要翻译：随机数发生器电路包括具有多个存储元件的第一存储器。当由施加到第一存储器的电压源供电时，每个存储元件具有与之对应的初始状态。第一存储器用于产生包括指示存储元件的相应初始状态的多个位的第一信号。随机数发生器电路还包括耦合到第一存储器的纠错电路。误差校正电路可操作以接收第一信号并且校正第一信号中的至少一个位，其在连续施加电力到第一存储器从而产生第二信号时不重复。第二信号是在连续向第一存储器施加电力时可重复的随机数。

9. 发明授权

US08023348B2 Method and apparatus for testing a memory device 有权
标题翻译：用于测试存储器件的方法和装置
公开(公告)号：US08023348B2
公开(公告)日：2011-09-20
申请号：US12443776
申请日：2007-10-29
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00
CPC分类号： G11C8/08 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/1202
摘要： Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.
摘要翻译：提供了用于测试半导体存储器件的技术。存储器件包括多个存储器单元和连接到存储器单元的多个行线和列线，用于选择性地访问一个或多个存储器单元。该方法包括以下步骤：将至少一个对应于待测试的存储器单元中的给定一个行的行中的至少一个施加第一电压，选择第一电压以强调第一电压的至少一个性能特征存储器件，所述第一电压不同于施加到所述给定行之一行的第二电压，用于在所述存储器件的正常操作期间访问所述存储器单元中的至少一个; 根据规定的测试参数锻炼记忆装置; 以及识别存储器件是否在测试参数的规定余量内可操作。

10. 发明申请

US20100131825A1 Memory Device with Error Correction Capability and Efficient Partial Word Write Operation 有权
标题翻译：具有纠错能力和高效部分字写入操作的存储器件
公开(公告)号：US20100131825A1
公开(公告)日：2010-05-27
申请号：US11994740
申请日：2007-04-26
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： H03M13/05 , G06F12/00 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1008
摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。存储器件被配置为执行至少部分字写入操作和读取操作，其中部分字写入操作包括读取阶段和写入阶段。部分字写入操作的写入阶段在存储器件的相同时钟周期中发生在与读取操作相同的时钟周期中，例如在部分字写入操作的写入相位与时钟周期内的存储器阵列的时间复用位线之间，读操作。因此，部分字写入操作对于包含或以其他方式利用存储器件的更高级系统出现，就好像该操作仅需要存储器件的单个时钟周期。

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