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1. 发明授权

US08566377B2 Secure random number generator 有权
标题翻译：安全随机数发生器
公开(公告)号：US08566377B2
公开(公告)日：2013-10-22
申请号：US12934510
申请日：2008-05-23
申请人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Edward B. Harris , Richard Hogg , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , G06F11/1008 , G11C11/412 , G11C2029/0411
摘要： A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.
摘要翻译：随机数发生器电路包括具有多个存储元件的第一存储器。当由施加到第一存储器的电压源供电时，每个存储元件具有与之对应的初始状态。第一存储器用于产生包括指示存储元件的相应初始状态的多个位的第一信号。随机数发生器电路还包括耦合到第一存储器的纠错电路。误差校正电路可操作以接收第一信号并且校正第一信号中的至少一个位，其在连续施加电力到第一存储器从而产生第二信号时不重复。第二信号是在连续向第一存储器施加电力时可重复的随机数。

2. 发明授权

US08023348B2 Method and apparatus for testing a memory device 有权
标题翻译：用于测试存储器件的方法和装置
公开(公告)号：US08023348B2
公开(公告)日：2011-09-20
申请号：US12443776
申请日：2007-10-29
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C29/00
CPC分类号： G11C8/08 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/1202
摘要： Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.
摘要翻译：提供了用于测试半导体存储器件的技术。存储器件包括多个存储器单元和连接到存储器单元的多个行线和列线，用于选择性地访问一个或多个存储器单元。该方法包括以下步骤：将至少一个对应于待测试的存储器单元中的给定一个行的行中的至少一个施加第一电压，选择第一电压以强调第一电压的至少一个性能特征存储器件，所述第一电压不同于施加到所述给定行之一行的第二电压，用于在所述存储器件的正常操作期间访问所述存储器单元中的至少一个; 根据规定的测试参数锻炼记忆装置; 以及识别存储器件是否在测试参数的规定余量内可操作。

3. 发明授权

US07948819B2 Integrated circuit having a memory with process-voltage-temperature control 有权
标题翻译：具有具有过程电压 - 温度控制的存储器的集成电路
公开(公告)号：US07948819B2
公开(公告)日：2011-05-24
申请号：US11860891
申请日：2007-09-25
申请人： Mathew R. Henry , Douglas D. Lopata , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
发明人： Mathew R. Henry , Douglas D. Lopata , Richard J. McPartland , Hai Quang Pham , Wayne E. Werner
IPC分类号： G11C7/22 , G11C8/18 , G11C7/04 , G11C7/02
CPC分类号： G11C7/04 , G11C7/22 , G11C2207/104
摘要： Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.
摘要翻译：本发明的某些实施例提供一种集成电路（IC），其具有可操作地耦合到PVT（过程电压 - 温度）源和可调节存储器的处理器。处理器从源头接收表征当前PVT条件的输入，并且基于该输入生成用于存储器的命令。响应于该命令，存储器调整其内部电路结构，时钟速度和/或工作电压以优化其对于当前PVT条件的性能。有利地，调整存储器以使其能够维持其功能并在不利的PVT条件下提供可接受的性能水平的能力在选择电路设计选项方面提供了额外的灵活性，其可以产生区域节省和/或增加可接受的IC的产量制造。

4. 发明申请

US20100131825A1 Memory Device with Error Correction Capability and Efficient Partial Word Write Operation 有权
标题翻译：具有纠错能力和高效部分字写入操作的存储器件
公开(公告)号：US20100131825A1
公开(公告)日：2010-05-27
申请号：US11994740
申请日：2007-04-26
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： H03M13/05 , G06F12/00 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1008
摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform at least a partial word write operation and a read operation, with the partial word write operation comprising a read phase and a write phase. The write phase of the partial word write operation occurs in the same clock cycle of the memory device as the read operation by, for example, time multiplexing bitlines of the memory array within the clock cycle between the write phase of the partial word write operation and the read operation. Thus, the partial word write operation appears to a higher-level system incorporating or otherwise utilizing the memory device as if that operation requires only a single clock cycle of the memory device.
摘要翻译：存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。存储器件被配置为执行至少部分字写入操作和读取操作，其中部分字写入操作包括读取阶段和写入阶段。部分字写入操作的写入阶段在存储器件的相同时钟周期中发生在与读取操作相同的时钟周期中，例如在部分字写入操作的写入相位与时钟周期内的存储器阵列的时间复用位线之间，读操作。因此，部分字写入操作对于包含或以其他方式利用存储器件的更高级系统出现，就好像该操作仅需要存储器件的单个时钟周期。

5. 发明申请

US20090196098A1 Multiple-Level Memory with Analog Read 有权
标题翻译：具有模拟读取功能的多级存储器
公开(公告)号：US20090196098A1
公开(公告)日：2009-08-06
申请号：US12023092
申请日：2008-01-31
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C27/005 , G11C7/06 , G11C11/5642 , G11C29/00
摘要： A memory circuit includes a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, and a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells. The circuit further includes multiple sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge. An analog multiplexer is connected to the sense amplifiers. The analog multiplexer is operative to receive the respective analog signals from the sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the sense amplifiers.
摘要翻译：存储器电路包括多个存储器单元，每个存储单元可操作以在其中存储多个数据位，并且多个列线和行线耦合到存储器单元以选择性地访问存储器单元。该电路还包括多个读出放大器，每个读出放大器连接到相应的列线之一，并且可操作以检测存储在耦合到对应的列线的存储器单元中选定的一个中的电荷，并产生指示所存储的电荷的模拟信号。模拟多路复用器连接到读出放大器。模拟多路复用器可操作以从读出放大器接收相应的模拟信号，并产生具有随时间变化的幅度的模拟输出信号，作为来自读出放大器的相应模拟信号的函数。

6. 发明申请

US20090141575A1 Method and Apparatus for Idle Cycle Refresh Request in Dram 有权
标题翻译：用于空闲周期刷新请求的方法和装置
公开(公告)号：US20090141575A1
公开(公告)日：2009-06-04
申请号：US11948214
申请日：2007-11-30
申请人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4065
摘要： Generally, methods and apparatus are provided for idle cycle refresh request in a dynamic random access memory. According to one aspect of the invention, a dynamic random access memory is refreshed by determining if a refresh of the dynamic random access memory is required; and allocating an idle cycle sequence to refresh at least a portion of the dynamic random access memory only if the determining step determines that a refresh of the dynamic random access memory is required. A refresh flag can optionally be set if a refresh is required. The idle cycle sequence comprises one or more idle cycles. The idle cycle sequence can optionally be allocated within a predefined duration of the refresh flag being set. The step of determining step whether a refresh of the dynamic random access memory is required can be based on real-time or expected conditions.
摘要翻译：通常，为动态随机存取存储器中的空闲周期刷新请求提供方法和装置。根据本发明的一个方面，通过确定是否需要刷新动态随机存取存储器来刷新动态随机存取存储器; 以及仅当确定步骤确定需要动态随机存取存储器的刷新时，才分配空闲周期序列来刷新动态随机存取存储器的至少一部分。如果需要刷新，可以选择设置刷新标志。空闲周期序列包括一个或多个空闲周期。空闲周期序列可以可选地在被设置的刷新标志的预定持续时间内被分配。确定步骤是否需要刷新动态随机存取存储器的步骤可以基于实时或预期的条件。

7. 发明申请

US20090034356A1 Dual-Port Memory 有权
标题翻译：双端口内存
公开(公告)号：US20090034356A1
公开(公告)日：2009-02-05
申请号：US11830417
申请日：2007-07-30
申请人： Donald Albert Evans , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
发明人： Donald Albert Evans , Ross A. Kohler , Richard J. McPartland , Wayne E. Werner
IPC分类号： G11C8/00
CPC分类号： G11C7/1075
摘要： A dual-port memory circuit includes a plurality of memory sub-blocks. Each of the memory sub-blocks includes a plurality of single-port memory cells, at least one row line, and at least one local bit line, the row line and the bit line being coupled to the memory cells for selectively accessing the memory cells. The memory circuit further includes at least one global bit line connected to the plurality of memory sub-blocks. The global bit line is time-multiplexed during a given memory cycle such that the global bit line propagates data associated with a first port in the memory circuit during a first portion of the memory cycle, and the global bit line propagates data associated with a second port in the memory circuit during a second portion of the memory cycle.
摘要翻译：双端口存储器电路包括多个存储器子块。每个存储器子块包括多个单端口存储器单元，至少一个行线和至少一个局部位线，行线和位线被耦合到存储器单元，以选择性地访问存储器单元。存储器电路还包括连接到多个存储器子块的至少一个全局位线。全局位线在给定存储器周期期间被时分多路复用，使得全局位线在存储器周期的第一部分期间传播与存储器电路中的第一端口相关联的数据，并且全局位线传播与第二在存储器循环的第二部分期间存储器电路中的端口。

8. 发明授权

US07295480B2 Semiconductor memory repair methodology using quasi-non-volatile memory 有权
标题翻译：使用准非易失性存储器的半导体存储器修复方法
公开(公告)号：US07295480B2
公开(公告)日：2007-11-13
申请号：US10739701
申请日：2003-12-18
申请人： Richard J. McPartland
发明人： Richard J. McPartland
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/4401 , G11C29/44 , G11C2029/0401
摘要： A device and method is provided for effecting soft repair of semiconductor memory embedded within an integrated circuit. The invention temporarily and in a non-volatile or quasi-non-volatile manner stores data within the structure of the semiconductor chip. This data respects chip performance at a first test point and may be made available directly from the chip at a second test point. In a particular embodiment of the invention, on-chip non-volatile memory is utilized to communicate reconfiguration codes between two testpoints for soft repair of SRAM and DRAM memory. A reconfiguration code generated for the first test point is stored in the on-chip non-volatile memory and read out from that memory at the second test point. Illustratively, the on-chip non-volatile memory is implemented as quasi-non-volatile memory. In a further embodiment, the invention operates to communicate the reconfiguration codes between a single wafer probe testpoint and a package testpoint.
摘要翻译：提供了一种用于对集成电路中嵌入的半导体存储器进行软修复的装置和方法。本发明暂时且以非易失性或准非易失性方式将数据存储在半导体芯片的结构内。该数据表示在第一测试点处的芯片性能，并且可以在第二测试点从芯片直接获得芯片性能。在本发明的特定实施例中，使用片上非易失性存储器来在两个测试点之间通信重配置码，用于软件修复SRAM和DRAM存储器。为第一测试点生成的重新配置代码存储在片上非易失性存储器中，并在第二个测试点从该存储器中读出。说明性地，片上非易失性存储器被实现为准非易失性存储器。在另一实施例中，本发明用于在单个晶片探针测试点和封装测试点之间传送重新配置代码。

9. 发明授权

US06552931B2 Low voltage flash EEPROM memory cell with improved data retention 有权
公开(公告)号：US06552931B2
公开(公告)日：2003-04-22
申请号：US09957124
申请日：2001-09-20
申请人： Richard J. McPartland , Ranbir Singh
发明人： Richard J. McPartland , Ranbir Singh
IPC分类号： G11C1604
CPC分类号： H01L27/115 , G11C16/0408 , G11C16/0416 , G11C2216/10
摘要： The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

10. 发明授权

US06191980B1 Single-poly non-volatile memory cell having low-capacitance erase gate 有权
标题翻译：具有低电容擦除栅极的单多晶非易失性存储单元
公开(公告)号：US06191980B1
公开(公告)日：2001-02-20
申请号：US09583505
申请日：2000-05-31
申请人： Patrick J. Kelley , Ross A. Kohler , Chung W. Leung , Richard J. McPartland , Ranbir Singh
发明人： Patrick J. Kelley , Ross A. Kohler , Chung W. Leung , Richard J. McPartland , Ranbir Singh
IPC分类号： G11C1604
CPC分类号： G11C16/0408 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A single-poly flash memory cell has a control device, a switch device, and an erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell is erased by applying an erase voltage to the tub of the erase device to cause tunneling across the oxide layer separating the floating gate from the rest of the erase device structure. Since a typical tub-to-source/drain breakdown voltage (e.g., 15 volts) is greater than a typical erase voltage (e.g., 10 volts), the memory cell can be safely erased without risking the junction breakdowns that are associated with other prior art single-poly memory cell designs for deep sub-micron technologies (e.g., 0.25-micron and lower).
摘要翻译：单聚焦闪存单元具有控制装置，开关装置和擦除装置，所有这些都共享共同的多晶硅浮动栅极，其被设计为在编程的存储器单元中保持电荷。通过向擦除装置的桶施加擦除电压来擦除存储器单元，以使隔离浮动栅极与擦除装置结构的其余部分的氧化物层的隧穿。由于典型的桶到源极/漏极击穿电压（例如15伏特）大于典型的擦除电压（例如，10伏特），所以可以安全地擦除存储器单元，而不会与与其它先前相关联的结点故障用于深亚微米技术（例如，0.25微米及更低）的单一多晶硅记忆体设计。

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