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1. 发明授权

US08792161B2 Optical polarizer with nanotube array 有权
标题翻译：具有纳米管阵列的光学偏振器
公开(公告)号：US08792161B2
公开(公告)日：2014-07-29
申请号：US11709718
申请日：2007-02-21
申请人： Bruno M. LaFontaine , Ryoung-Han Kim , Harry J. Levinson , Uzodinma Okoroanyanwu
发明人： Bruno M. LaFontaine , Ryoung-Han Kim , Harry J. Levinson , Uzodinma Okoroanyanwu
IPC分类号： G02B5/30
CPC分类号： G02B5/3058 , G02B5/3075 , G02F1/0136 , G03F7/70566
摘要： An optical polarizer positioned before a light source for use in semiconductor wafer lithography including an array of aligned nanotubes. The array of aligned nanotubes cause light emitted from the light source and incident on the array of aligned nanotubes to be converted into polarized light for use in the semiconductor wafer lithography. The amount of polarization can be controlled by a voltage source coupled to the array of aligned nanotubes. Chromogenic material of a light filtering layer can vary the wavelength of the polarized light transmitted through the array of aligned nanotubes.
摘要翻译：位于用于半导体晶片光刻的光源之前的光学偏振器，包括排列的纳米管阵列。排列的纳米管的阵列引起从光源发射并入射到排列的纳米管阵列上的光，以转换为偏光，用于半导体晶片光刻。极化量可以通过耦合到排列的纳米管阵列的电压源来控制。光过滤层的显色材料可以改变通过排列的纳米管阵列传输的偏振光的波长。

2. 发明授权

US08586269B2 Method for forming a high resolution resist pattern on a semiconductor wafer 有权
标题翻译：在半导体晶片上形成高分辨率抗蚀剂图案的方法
公开(公告)号：US08586269B2
公开(公告)日：2013-11-19
申请号：US11726433
申请日：2007-03-22
申请人： Uzodinma Okoroanyanwu , Harry J. Levinson , Ryoung-Han Kim , Thomas Wallow
发明人： Uzodinma Okoroanyanwu , Harry J. Levinson , Ryoung-Han Kim , Thomas Wallow
IPC分类号： G11B11/105
CPC分类号： G03F7/38
摘要： In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent.
摘要翻译：在一个公开的实施例中，在半导体晶片上形成高分辨率抗蚀剂图案的方法包括在半导体晶片上形成的材料层上形成包含例如聚合物基质和催化物质的抗蚀剂层; 将抗蚀剂层暴露于图案化辐射; 以及在后曝光烘烤处理期间向半导体晶片施加磁场。在一个实施例中，图案化的辐射由极紫外（EUV）光源提供。在其它实施例中，图案化辐射源可以是例如电子束或离子束。在一个实施方案中，聚合物基质是有机聚合物基质，例如苯乙烯，丙烯酸酯或甲基丙烯酸酯。在一个实施方案中，催化物质可以是例如酸，碱或氧化剂。

3. 发明授权

US07718529B2 Inverse self-aligned spacer lithography 有权
标题翻译：反向自对准间隔光刻
公开(公告)号：US07718529B2
公开(公告)日：2010-05-18
申请号：US11778852
申请日：2007-07-17
申请人： Yunfei Deng , Ryoung-han Kim , Thomas I. Wallow
发明人： Yunfei Deng , Ryoung-han Kim , Thomas I. Wallow
IPC分类号： H01L21/00
CPC分类号： H01L21/0337 , Y10S438/947
摘要： Ultrafine dimensions, smaller than conventional lithographic capabilities, are formed employing an efficient inverse spacer technique comprising selectively removing spacers. Embodiments include forming a first mask pattern over a target layer, forming a spacer layer on the upper and side surfaces of the first mask pattern leaving intermediate spaces, depositing a material in the intermediate spacers leaving the spacer layer exposed, selectively removing the spacer layer to form a second mask pattern having openings exposing the target layer, and etching the target layer through the second mask pattern.
摘要翻译：采用有选择地去除间隔物的有效的逆间隔技术来形成小于常规光刻能力的超细尺寸。实施例包括在目标层上形成第一掩模图案，在第一掩模图案的上表面和侧表面上形成间隔层，留下中间空间，在间隔层暴露的中间间隔物中沉积材料，选择性地除去间隔层，形成具有暴露目标层的开口的第二掩模图案，并且通过第二掩模图案蚀刻目标层。

4. 发明申请

US20090040483A1 MULTIPLE EXPOSURE TECHNIQUE USING OPC TO CORRECT DISTORTION 有权
标题翻译：使用OPC纠正错误的多次曝光技术
公开(公告)号：US20090040483A1
公开(公告)日：2009-02-12
申请号：US11834979
申请日：2007-08-07
申请人： Yunfei Deng , Jongwook Kye , Ryoung-han Kim
发明人： Yunfei Deng , Jongwook Kye , Ryoung-han Kim
IPC分类号： G03B27/42 , G03B27/68
CPC分类号： G03B27/42
摘要： Accurate ultrafine patterns are formed using a multiple exposure technique comprising implementing an OPC procedure to form an exposure reticle to compensate for distortion of an overlying resist pattern caused by an underlying resist pattern. Embodiments include forming a first resist pattern in a first resist layer over a target layer using a first exposure reticle, forming a second exposure reticle by an OPC technique to compensate for distortion of a second resist pattern caused by the underlying first resist pattern, depositing a second resist layer on the first resist pattern, forming the second resist pattern in the second resist layer using the second exposure reticle, the first and second resist patterns constituting a final resist mask, and forming a pattern in the target layer using the final resist mask.
摘要翻译：使用多重曝光技术形成精确的超细纹图案，该技术包括实施OPC程序以形成曝光掩模版，以补偿由下面的抗蚀剂图案引起的上覆抗蚀剂图案的变形。实施例包括使用第一曝光掩模在目标层上在第一抗蚀剂层中形成第一抗蚀剂图案，通过OPC技术形成第二曝光掩模版，以补偿由下面的第一抗蚀剂图案引起的第二抗蚀剂图案的变形，在第一抗蚀剂图案上的第二抗蚀剂层，使用第二曝光掩模在第二抗蚀剂层中形成第二抗蚀剂图案，第一和第二抗蚀剂图案构成最终抗蚀剂掩模，并且使用最终抗蚀剂掩模在目标层中形成图案。

5. 发明申请

US20080171446A1 METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20080171446A1
公开(公告)日：2008-07-17
申请号：US11623031
申请日：2007-01-12
申请人： Ryoung-han Kim , Thomas Ingolf Wallow , Harry Jay Levinson , Jongwook Kye , Alden R. Acheta
发明人： Ryoung-han Kim , Thomas Ingolf Wallow , Harry Jay Levinson , Jongwook Kye , Alden R. Acheta
IPC分类号： H01L21/31
CPC分类号： H01L21/0273 , G03F7/40 , H01L21/0338
摘要： A method for forming a semiconductor device is provided including processing a wafer having a target material; forming a first pattern over the target material; forming a protection layer over the first pattern; and forming a second pattern, over the target material and not over the protection layer, without an etching step between the forming the first pattern and the forming the second pattern.
摘要翻译：提供一种形成半导体器件的方法，包括处理具有目标材料的晶片; 在目标材料上形成第一图案; 在所述第一图案上形成保护层; 并且在形成第一图案和形成第二图案之间没有蚀刻步骤的情况下，在目标材料上形成第二图案而不是在保护层上方。

6. 发明申请

US20120058640A1 METHOD FOR FORMING AN INTERCONNECT STRUCTURE 有权
标题翻译：形成互连结构的方法
公开(公告)号：US20120058640A1
公开(公告)日：2012-03-08
申请号：US12876510
申请日：2010-09-07
申请人： Ryoung-Han Kim , Matthew E. Colburn
发明人： Ryoung-Han Kim , Matthew E. Colburn
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31144
摘要： A method for forming an interconnect structure includes forming a mandrel above a base layer, forming spacers on the mandrel, forming recesses in the base layer using the spacers as an etch template, and forming a conductive material in the recesses.
摘要翻译：用于形成互连结构的方法包括在基底层上形成心轴，在心轴上形成间隔物，使用间隔物作为蚀刻模板在基底层中形成凹陷，并在凹部中形成导电材料。

7. 发明申请

US20120043646A1 SPACER DOUBLE PATTERNING THAT PRINTS MULTIPLE CD IN FRONT-END-OF-LINE 有权
标题翻译：在前端打印多张CD的间隔双重图案
公开(公告)号：US20120043646A1
公开(公告)日：2012-02-23
申请号：US12860327
申请日：2010-08-20
申请人： Ryoung-han Kim
发明人： Ryoung-han Kim
IPC分类号： H01L21/306 , H01L29/02
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions. Embodiments further include using a third mask to form a semiconductor device having further features with a different critical dimension, but the same pitch, as the sub-resolution features.
摘要翻译：半导体器件形成有子分辨率特征，并且至少一个附加特征具有仅使用两个掩模的相对较大的临界尺寸。一个实施例包括形成具有第一宽度的多个第一心轴和具有大于第一宽度的第二宽度的至少一个第二心轴，使用第一掩模覆盖目标层，沿着第一宽度的长度和宽度形成侧壁间隔物所述第一和第二心轴在每个侧壁间隔物附近形成填料，所述填料具有第一宽度，使用第二掩模，沿着所述第一和第二心轴的宽度除去所述填料相邻的侧壁间隔物，去除所述侧壁间隔物，并蚀刻所述靶填充物与第一和第二心轴之间的层，从而形成具有不同临界尺寸的至少两个目标特征。实施例还包括使用第三掩模来形成半导体器件，该半导体器件具有与子分辨特征具有不同临界尺寸但具有相同间距的另外特征。

8. 发明授权

US08009274B2 In-die focus monitoring with binary mask 有权
标题翻译：二进制掩码的管芯内聚焦监控
公开(公告)号：US08009274B2
公开(公告)日：2011-08-30
申请号：US12167808
申请日：2008-07-03
申请人： Ryoung-han Kim
发明人： Ryoung-han Kim
IPC分类号： G03B27/52 , G03B27/68
CPC分类号： G03B27/52 , G03F7/70641
摘要： Focus monitoring for a photolithographic applications is provided by illuminating a photoresist layer with a light beam transmitted through a first binary mask to define a circuit pattern on an underlying substrate and then illuminating the photoresist layer with an unbalanced off-axis light beam transmitted through a second binary mask. The second mask contains a shifting feature configuration in one portion, while another portion blocks light transmission to the chip design area of the photoresist. After development of the photoresist layer, the pattern formed by illumination of the second mask can be compared with a predefined reference feature on the photoresist layer to determine whether a shift, if any, is within acceptable focus limits.
摘要翻译：通过用透射通过第一二进制掩模的光束照射光致抗蚀剂层来限定在下面的衬底上的电路图案，然后用不平衡的离轴光束照射光致抗蚀剂层来提供用于光刻应用的聚焦监控，所述非平衡离轴光束透射通过第二二进制掩码第二掩模包含一部分中的移动特征构造，而另一部分遮挡到光致抗蚀剂的芯片设计区域的光透射。在光致抗蚀剂层的显影之后，通过第二掩模的照射形成的图案可以与光致抗蚀剂层上的预定参考特征进行比较，以确定移位（如果有的话）是否在可接受的聚焦限度内。

9. 发明申请

US20110014790A1 METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110014790A1
公开(公告)日：2011-01-20
申请号：US12505961
申请日：2009-07-20
申请人： Ryoung-Han KIM
发明人： Ryoung-Han KIM
IPC分类号： H01L21/308
CPC分类号： H01L21/0273 , H01L21/0337 , H01L21/0338
摘要： Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In one embodiment, a method comprises the steps of forming etch masking features overlying the semiconductor substrate, the etch masking features having a first thickness, and forming an etch barrier layer overlying the substrate, the etch barrier layer having a second thickness less than or substantially equal to the first thickness. The method also comprises removing the etch masking features to expose the substrate, and etching the substrate using the etch barrier layer as an etch mask.
摘要翻译：提供了用于在半导体衬底上和半导体衬底中制造半导体器件的方法。在一个实施例中，一种方法包括以下步骤：形成覆盖半导体衬底的蚀刻掩模特征，蚀刻掩模特征具有第一厚度，以及形成覆盖衬底的蚀刻阻挡层，蚀刻阻挡层具有小于或基本上等于第一厚度。该方法还包括去除蚀刻掩模特征以暴露衬底，以及使用蚀刻阻挡层作为蚀刻掩模蚀刻衬底。

10. 发明申请

US20100270652A1 DOUBLE EXPOSURE TECHNOLOGY USING HIGH ETCHING SELECTIVITY 有权
标题翻译：使用高蚀刻选择性的双重曝光技术
公开(公告)号：US20100270652A1
公开(公告)日：2010-10-28
申请号：US12762457
申请日：2010-04-19
申请人： Ryoung-Han Kim , Jong-wook Kye
发明人： Ryoung-Han Kim , Jong-wook Kye
IPC分类号： H01L23/00
CPC分类号： G03F7/0035 , G03F1/70 , G03F7/70466
摘要： Ultrafine patterns with dimensions smaller than the chemical and optical limits of lithography are formed by superimposing two photoresist patterns using a double exposure technique. Embodiments include forming a first resist pattern over a target layer to be patterned, forming a protective cover layer over the first resist pattern, forming a second resist pattern on the cover layer superimposed over the first resist pattern while the cover layer protects the first resist pattern, selectively etching the cover layer with high selectivity with respect to the first and second resist patterns leaving an ultrafine target pattern defined by the first and second resist patterns, and etching the underlying target layer using the superimposed first and second resist patterns as a mask.
摘要翻译：尺寸小于光刻的化学和光学限制的超细图案通过使用双曝光技术叠加两个光致抗蚀剂图案来形成。实施例包括在待图案化的目标层上形成第一抗蚀剂图案，在第一抗蚀剂图案上方形成保护覆盖层，在叠层在第一抗蚀剂图案上的覆盖层上形成第二抗蚀剂图案，同时覆盖层保护第一抗蚀剂图案以相对于第一和第二抗蚀剂图案的高选择性选择性地蚀刻覆盖层，留下由第一和第二抗蚀剂图案限定的超细目标图案，并使用叠加的第一和第二抗蚀剂图案作为掩模蚀刻下面的目标层。

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