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    • 2. 发明申请
    • Integrated circuit and method for automatically tuning process and temperature variations
    • 用于自动调节过程和温度变化的集成电路和方法
    • US20070090870A1
    • 2007-04-26
    • US11437649
    • 2006-05-22
    • Sung-jae JungSang-yoon Jeon
    • Sung-jae JungSang-yoon Jeon
    • H01L35/00
    • G01R31/31704G01R31/317
    • Provided are an IC and a method for automatically tuning process and temperature variations. The IC includes: a test circuit unit including test circuit elements having identical element values and variations to a tuning-targeted circuit element and at least one reference circuit element having a smaller variation than the tuning-targeted circuit element; a comparator that obtains a difference between intensities of first and second signals detected from the test circuit unit; and a tuning unit that tunes the variation of the tuning-targeted circuit element according to the difference between the intensities of the first and second signals. Thus, process and temperature variations of a circuit element can be detected and accurately tuned with respect to the circuit element itself. Also, the process and temperature variations can be tuned inside an IC. Thus, the time required for tuning the process and temperature variations can be reduced.
    • 提供了一种用于自动调整过程和温度变化的IC和方法。 IC包括:测试电路单元,包括具有与调谐目标电路元件相同的元件值和变化的测试电路元件以及具有比调谐目标电路元件更小变化的至少一个参考电路元件; 获得从测试电路单元检测到的第一和第二信号的强度之间的差的比较器; 以及调谐单元,其根据第一和第二信号的强度之间的差调谐调谐目标电路元件的变化。 因此,可以相对于电路元件本身检测并精确地调谐电路元件的工艺和温度变化。 此外,可以在IC内部调整过程和温度变化。 因此,可以减少调整过程和温度变化所需的时间。
    • 4. 发明申请
    • Dual gate cascade amplifier
    • 双门级联放大器
    • US20050073366A1
    • 2005-04-07
    • US10956082
    • 2004-10-04
    • Sung-jae JungHoon-tae KimYun-seong EoKwang-du LeeSang-yoon Jeon
    • Sung-jae JungHoon-tae KimYun-seong EoKwang-du LeeSang-yoon Jeon
    • H01L27/02H01L27/07H03F1/22
    • H03F1/223H01L27/0207H01L27/0705
    • A dual gate cascade amplifier includes a first transistor and a second transistor electrically connected in series, the second transistor including a first parallel transistor and a second parallel transistor, the first parallel transistor and the second parallel transistor being electrically connected in parallel, a first channel electrically connecting a first end channel region of the first transistor and a second end channel region, wherein one of the first or second end channel regions is a source and the other of the first or second end channel regions is a drain, the second end channel region being a common end channel region shared by the first and second parallel transistors, and a second channel electrically connected to the second end channel region and extending away from the first transistor.
    • 双栅级联放大器包括串联电连接的第一晶体管和第二晶体管,第二晶体管包括第一并联晶体管和第二并联晶体管,第一并联晶体管和第二并联晶体管并联电连接,第一沟道 电连接第一晶体管的第一端部沟道区域和第二端部沟道区域,其中第一或第二端部沟道区域之一是源极,并且第一或第二端部沟道区域中的另一个是漏极,第二端部通道 区域是由第一和第二并联晶体管共享的公共末端通道区域,以及电连接到第二端部通道区域并远离第一晶体管延伸的第二通道。
    • 5. 发明授权
    • NxN multiple-input multiple-output transceiver
    • NxN多输入多输出收发器
    • US07848435B2
    • 2010-12-07
    • US11543120
    • 2006-10-05
    • Sang-yoon JeonHee-mun BangSung-jae JungHeung-bae Lee
    • Sang-yoon JeonHee-mun BangSung-jae JungHeung-bae Lee
    • H04L1/02
    • H04B7/0413H04L1/06
    • An N×N multiple-input multiple-output (MIMO) transceiver is provided. The transceiver includes a plurality of transceivers, each including at least one transceiver circuit; an oscillation unit which is configured to generate a differential signal which is supplied to the at least one transceiver circuit; a plurality of buffers, which are mounted in a bypass line between the at least one transceiver circuit and the oscillation unit and are configured to amplify and bypass the differential signal or input and amplify the differential signal; and a buffer control unit which is configured to control the plurality of buffers to bypass or input the differential signal.
    • 提供了一种N×N多输入多输出(MIMO)收发器。 收发器包括多个收发器,每个收发器包括至少一个收发器电路; 振荡单元,被配置为生成提供给所述至少一个收发器电路的差分信号; 多个缓冲器,其安装在所述至少一个收发器电路和所述振荡单元之间的旁路线路中,并且被配置为放大和旁路所述差分信号或者输入和放大所述差分信号; 以及缓冲器控制单元,其被配置为控制所述多个缓冲器来旁路或输入所述差分信号。
    • 7. 发明授权
    • Dual-band voltage-controlled oscillator using bias switching and output-buffer multiplexing
    • 双频压控振荡器采用偏置开关和输出缓冲复用
    • US07414490B2
    • 2008-08-19
    • US11288212
    • 2005-11-29
    • Sang-yoon JeonHeung-bae LeeSeong-soo LeeJinup LimJoongho Choi
    • Sang-yoon JeonHeung-bae LeeSeong-soo LeeJinup LimJoongho Choi
    • H03B5/12
    • H03B5/1228H03B5/1209H03B5/1215H03B5/124
    • Disclosed is a dual-band voltage-controlled oscillator using bias switching and output-buffer multiplexing. The dual-band voltage-controlled oscillator includes a power supply unit for supplying a source voltage; plural voltage-controlled oscillation units for outputting different oscillation frequencies according to controls of a certain tuning voltage; plural bias units for generating driving voltages for driving the voltage-controlled oscillation units and supplying the driving voltages to the voltage-controlled oscillation units; and plural buffers for selectively outputting oscillation frequencies of the plural voltage-controlled oscillation units. The present invention implements the dual-band voltage-controlled oscillator through bias switching and output-buffer multiplexing, which brings an advantage of elimination of interference between output frequencies to enhance phase noise characteristics.
    • 公开了一种使用偏置开关和输出缓冲器复用的双频带压控振荡器。 双频带压控振荡器包括用于提供源电压的电源单元; 多个电压控制振荡单元,用于根据某个调谐电压的控制输出不同的振荡频率; 多个偏压单元,用于产生用于驱动压控振荡单元的驱动电压并将驱动电压提供给压控振荡单元; 以及用于选择性地输出多个压控振荡单元的振荡频率的多个缓冲器。 本发明通过偏置开关和输出缓冲多路复用来实现双频压控振荡器,其具有消除输出频率之间的干扰以增强相位噪声特性的优点。
    • 9. 发明授权
    • Dual gate cascade amplifier
    • 双门级联放大器
    • US07199669B2
    • 2007-04-03
    • US10956082
    • 2004-10-04
    • Sung-jae JungHoon-tae KimYun-seong EoKwang-du LeeSang-yoon Jeon
    • Sung-jae JungHoon-tae KimYun-seong EoKwang-du LeeSang-yoon Jeon
    • H03F3/04
    • H03F1/223H01L27/0207H01L27/0705
    • A dual gate cascade amplifier includes a first transistor and a second transistor electrically connected in series, the second transistor including a first parallel transistor and a second parallel transistor, the first parallel transistor and the second parallel transistor being electrically connected in parallel, a first channel electrically connecting a first end channel region of the first transistor and a second end channel region, wherein one of the first or second end channel regions is a source and the other of the first or second end channel regions is a drain, the second end channel region being a common end channel region shared by the first and second parallel transistors, and a second channel electrically connected to the second end channel region and extending away from the first transistor.
    • 双栅级联放大器包括串联电连接的第一晶体管和第二晶体管,第二晶体管包括第一并联晶体管和第二并联晶体管,第一并联晶体管和第二并联晶体管并联电连接,第一沟道 电连接第一晶体管的第一端部沟道区域和第二端部沟道区域,其中第一或第二端部沟道区域之一是源极,并且第一或第二端部沟道区域中的另一个是漏极,第二端部通道 区域是由第一和第二并联晶体管共享的公共末端通道区域,以及电连接到第二端部通道区域并远离第一晶体管延伸的第二通道。