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1. 发明授权

US09312016B2 Multi-level cell memory device and method of operating multi-level cell memory device 有权
标题翻译：多级单元存储器件和操作多级单元存储器件的方法
公开(公告)号：US09312016B2
公开(公告)日：2016-04-12
申请号：US14135734
申请日：2013-12-20
申请人： Kyungryun Kim , Sangyong Yoon
发明人： Kyungryun Kim , Sangyong Yoon
IPC分类号： G11C11/56 , G11C16/26 , H01L29/792 , H01L27/115 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , H01L27/11582 , H01L29/7926
摘要： A read method of a multi-level cell memory device includes receiving a first read command, and reading first and second hard decision data by performing first and second hard decision read operations using a first hard decision read voltage and a second hard decision read voltage, respectively, the second hard decision read voltage being higher than the first hard decision read voltage. The method further includes selecting one of the first and second hard decision read voltages, reading first soft decision data by performing a first soft decision read operation using a plurality of soft decision read voltages having voltage levels which are different from that of the selected one of the first and second hard decision read voltages, and providing the first soft decision data to a memory controller for first error correction code (ECC) decoding.
摘要翻译：多级单元存储器件的读取方法包括接收第一读取命令，以及通过使用第一硬判决读取电压和第二硬判决读取电压执行第一和第二硬判决读取操作来读取第一和第二硬判决数据，第二硬判决读取电压分别高于第一硬判决读电压。该方法还包括选择第一和第二硬判决读取电压中的一个，通过使用多个软判决读取电压执行第一软判决读取操作来读取第一软判决数据，所述软判决读取电压具有不同于所选择的一个第一和第二硬判定读取电压，并且向存储器控制器提供第一软判决数据用于第一纠错码（ECC）解码。

2. 发明申请

US20160004437A1 STORAGE DEVICE AND READ METHODS THEREOF 有权
标题翻译：存储器件及其读取方法
公开(公告)号：US20160004437A1
公开(公告)日：2016-01-07
申请号：US14736484
申请日：2015-06-11
申请人： YOON KIM , KYEHYUN KYUNG , KYUNGRYUN KIM , SANGYONG YOON
发明人： YOON KIM , KYEHYUN KYUNG , KYUNGRYUN KIM , SANGYONG YOON
IPC分类号： G06F3/06 , G11C16/04 , G11C16/26 , G11C16/32 , G06F11/10 , G11C29/52
CPC分类号： G06F3/061 , G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F11/1048 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C29/021 , G11C29/023 , G11C29/028 , G11C29/52
摘要： A read method of a storage device includes performing a first read operation on a nonvolatile memory device based on a time stamp table storing a program time and a time-read level look-up table indicating a read level shift due to a program lapsed time. A determination is made whether to adjust the time-read level look-up table based on a result of the first read operation. As a consequence of determining to adjust the time-read level look-up table, adjusting the time-read level look-up table through a valley search operation and performing a second read operation on the nonvolatile memory device based on the time stamp table and the adjusted time-read level look-up table.
摘要翻译：存储装置的读取方法包括：基于存储程序时间的时间戳表和指示由于程序经过时间引起的读取电平移位的时间读取级别查找表，对非易失性存储器件执行第一读取操作。确定是否基于第一读取操作的结果来调整时间读取级别查找表。作为确定调整时间读取级别查找表的结果，通过谷值搜索操作来调整时间读取级别查找表，并且基于时间戳表对非易失性存储器设备执行第二读取操作，以及调整后的时间读取级别查找表。

3. 发明授权

US08976587B2 Data storage system having multi-bit memory device and operating method thereof 有权
标题翻译：具有多位存储装置的数据存储系统及其操作方法
公开(公告)号：US08976587B2
公开(公告)日：2015-03-10
申请号：US13737140
申请日：2013-01-09
申请人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
发明人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
IPC分类号： G11C16/04 , G11C16/10 , G11C11/56 , G11C16/26 , G11C14/00
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C14/0018 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： The operating method of a data storage device includes storing data in a buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of a memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to a multi-bit memory device based on the determined program pattern.
摘要翻译：数据存储装置的操作方法包括根据外部请求将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是伴随存储器单元阵列的缓冲器程序操作的数据。当存储在缓冲存储器中的数据是与缓冲器程序操作相关的数据时，该方法还包括确定是否需要对存储单元阵列的主程序操作，以及当需要存储单元阵列的主程序操作时，存储单元阵列中的主程序操作的程序模式。该方法还包括基于所确定的程序模式向存储器单元阵列发出用于主程序操作的一组命令到多位存储器件。

4. 发明授权

US08812933B2 Memory system and operating method thereof 有权
标题翻译：存储系统及其操作方法
公开(公告)号：US08812933B2
公开(公告)日：2014-08-19
申请号：US13449501
申请日：2012-04-18
申请人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jinman Han
发明人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jinman Han
IPC分类号： G06F11/00 , G11C29/00 , H03M13/00 , G11C11/34 , G11C8/00 , G06F11/10 , G06F11/08 , H03M13/15
CPC分类号： G06F11/1016 , G06F11/08 , G06F11/10 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F11/1076 , G06F11/108 , G11C11/5628 , G11C16/10 , G11C16/3418 , H03M13/151 , H03M13/1525 , H03M13/1545
摘要： A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device.
摘要翻译：存储器系统包括非易失性存储器件和存储器控制器，其被配置为控制非易失性存储器件并且被配置为向非易失性存储器件提供包括从非易失性存储器件读取的数据的错误的错误位置信息的错误标志信息。

5. 发明申请

US20140153331A1 MULTI-LEVEL CELL MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：多电平存储器件及其操作方法
公开(公告)号：US20140153331A1
公开(公告)日：2014-06-05
申请号：US14096281
申请日：2013-12-04
申请人： Joonsuc JANG , Sangyong YOON
发明人： Joonsuc JANG , Sangyong YOON
IPC分类号： G11C16/26 , G11C16/10
CPC分类号： G11C16/26 , G11C7/1039 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/102 , H01L27/1157 , H01L27/11582
摘要： According to an example embodiment of inventive concepts, an operating method of a non-volatile memory device includes: performing a first hard decision read operation that includes applying a first voltage if a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch.
摘要翻译：根据发明构思的示例性实施例，非易失性存储器件的操作方法包括：执行第一硬判决读取操作，其包括如果所述非易失性存储器件的所选择的字线施加第一电压; 将所述第一硬判决读取操作的结果存储在所述非易失性存储器件中的页缓冲器的第一锁存器处; 执行包括对选择的字线施加第二电压的第二硬判决读取操作，所述第二电压高于所述第一电压; 以及使用存储在所述第一锁存器处的所述第一硬判决读取操作的结果来生成第一软判决值。

6. 发明申请

US20140223246A1 MEMORY, MEMORY CONTROLLER, MEMORY SYSTEM, METHOD OF MEMORY, MEMORY CONTROLLER AND MEMORY SYSTEM 有权
标题翻译：存储器，存储控制器，存储器系统，存储器方法，存储器控制器和存储器系统
公开(公告)号：US20140223246A1
公开(公告)日：2014-08-07
申请号：US14147063
申请日：2014-01-03
申请人： Kyungryun KIM , Sangyong YOON
发明人： Kyungryun KIM , Sangyong YOON
IPC分类号： G11C29/50
CPC分类号： G11C11/5642 , G06F11/1012 , G06F11/1048 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C29/028 , G11C2211/5644 , H01L27/11578 , H03M13/373
摘要： In one embodiment, the method includes performing a read operation on a memory, and determining, by a memory controller, whether to perform a reliability verification read operation based on a count value and a reference value. The count value is based on a number of read commands issued by the memory controller to the memory, and the reliability verification read operation is for reading data from at least one memory cell associated with at least one unselected word line in the memory. An unselected word line is a word line not selected during the read operation. The method further includes performing the reliability verification read operation for the at least one unselected word line based on the determining.
摘要翻译：在一个实施例中，该方法包括对存储器执行读取操作，并且由存储器控制器确定是否基于计数值和参考值执行可靠性验证读取操作。计数值基于由存储器控制器发送到存储器的读取命令的数量，并且可靠性验证读取操作用于从与存储器中的至少一个未选择字线相关联的至少一个存储器单元读取数据。未选择的字线是在读取操作期间未被选择的字线。所述方法还包括基于所述确定对所述至少一个未选择字线执行所述可靠性验证读取操作。

7. 发明申请

US20130138870A1 MEMORY SYSTEM, DATA STORAGE DEVICE, MEMORY CARD, AND SSD INCLUDING WEAR LEVEL CONTROL LOGIC 审中-公开
标题翻译：存储系统，数据存储设备，存储卡和固态硬盘，包括磨损级控制逻辑
公开(公告)号：US20130138870A1
公开(公告)日：2013-05-30
申请号：US13604780
申请日：2012-09-06
申请人： SANGYONG YOON , CHULHO LEE , KYEHYUN KYUNG , JAEYONG JEONG
发明人： SANGYONG YOON , CHULHO LEE , KYEHYUN KYUNG , JAEYONG JEONG
IPC分类号： G06F12/02
CPC分类号： G11C16/06 , G06F11/1072 , G06F12/0246 , G06F2212/7211 , G11C11/5621 , G11C16/349 , G11C16/3495 , G11C2029/0411
摘要： Disclosed is a memory system which includes a nonvolatile memory having a user area and a buffer area; and wear level control logic managing a mode change operation in which memory blocks of the user area are partially changed into the buffer area, based on wear level information of the nonvolatile memory.
摘要翻译：公开了一种包括具有用户区域和缓冲区域的非易失性存储器的存储器系统; 以及磨损水平控制逻辑，其基于所述非易失性存储器的磨损水平信息，管理其中所述用户区域的存储块被部分地改变为所述缓冲区域的模式改变操作。

8. 发明授权

US08427871B2 Nonvolatile memory device, memory system incorporating same, and method of operating same 有权
标题翻译：非易失性存储器件，并入其的存储器系统及其操作方法
公开(公告)号：US08427871B2
公开(公告)日：2013-04-23
申请号：US12820435
申请日：2010-06-22
申请人： Jinman Han , Sangyong Yoon
发明人： Jinman Han , Sangyong Yoon
IPC分类号： G11C16/06
CPC分类号： G11C16/3459 , G06F11/1048 , G11C16/0483 , G11C16/3422
摘要： A nonvolatile memory device performs a program operation comprising applying a program pulse to selected memory cells, detecting a number of fail bits among the selected memory cells, the fail bits comprising failed program bits and disturbed inhibit bits, and determining a program completion status of the program operation based on the number of detected fail bits.
摘要翻译：非易失性存储器件执行程序操作，包括将程序脉冲施加到所选择的存储器单元，检测所选存储单元中的故障位数，失败位包括失败的程序位和受干扰的禁止位，以及确定程序完成状态基于检测到的故障位的数量进行编程操作。

9. 发明授权

US08339854B2 Nonvolatile memory device and data randomizing method thereof 有权
标题翻译：非易失性存储器件及其数据随机化方法
公开(公告)号：US08339854B2
公开(公告)日：2012-12-25
申请号：US12752255
申请日：2010-04-01
申请人： Sangyong Yoon
发明人： Sangyong Yoon
IPC分类号： G11C11/34
CPC分类号： G11C16/102 , G11C7/1006 , G11C11/5628 , G11C16/10 , G11C2216/14
摘要： A method is for operating a nonvolatile memory device, where the memory device includes a memory cell array and a page buffer block. The method includes loading program data into the page buffer block, loading random sequence data into the page buffer block, generating randomized data by executing a logic operation, such as a bit-wise XOR operation, in the page buffer circuit on the program data and the first random sequence data, and programming the randomized data into the memory cell array.
摘要翻译：一种用于操作非易失性存储器件的方法，其中存储器件包括存储单元阵列和页缓冲器块。该方法包括将程序数据加载到页面缓冲器块中，将随机序列数据加载到页面缓冲器块中，通过在页面缓冲器电路中对程序数据执行诸如逐位异或运算之类的逻辑运算来产生随机数据，以及第一个随机序列数据，并将随机数据编程到存储单元阵列中。

10. 发明申请

US20110222342A1 DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：具有多位存储器件的数据存储系统及其操作方法
公开(公告)号：US20110222342A1
公开(公告)日：2011-09-15
申请号：US13040295
申请日：2011-03-04
申请人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
发明人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C14/0018 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern.
摘要翻译：数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器并且控制非易失性存储器件的存储器控制器。数据存储装置的操作方法包括根据外部请求将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是与存储单元阵列的缓冲器程序操作相关的数据。当存储在缓冲存储器中的数据是伴随缓冲器程序操作的数据时，该方法还包括确定是否需要对存储单元阵列执行主程序操作，并且当需要存储单元阵列的主程序操作时，存储单元阵列中的主程序操作的程序模式。该方法还包括基于所确定的程序模式向存储器单元阵列发出用于主程序操作的一组命令给多位存储器件。

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