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1. 发明授权

US09665518B2 Methods and systems for controlling ordered write transactions to multiple devices using switch point networks 有权
公开(公告)号：US09665518B2
公开(公告)日：2017-05-30
申请号：US14495096
申请日：2014-09-24
申请人： Sanjay R. Deshpande , Mark A. Banse , John E. Larson , Fernando A. Morales , Thang Q. Nguyen
发明人： Sanjay R. Deshpande , Mark A. Banse , John E. Larson , Fernando A. Morales , Thang Q. Nguyen
IPC分类号： G06F13/00 , G06F13/36 , G06F13/40 , G06F13/16
CPC分类号： G06F13/4022 , G06F13/1621
摘要： Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.

2. 发明申请

US20160085478A1 Piggy-Back Snoops For Non-Coherent Memory Transactions Within Distributed Processing Systems 有权
标题翻译：在分布式处理系统中的非相干存储器事务的捎带侦察
公开(公告)号：US20160085478A1
公开(公告)日：2016-03-24
申请号：US14495209
申请日：2014-09-24
申请人： Sanjay R. Deshpande , John E. Larson , Fernando A. Morales , Thang Q. Nguyen , Mark A. Banse
发明人： Sanjay R. Deshpande , John E. Larson , Fernando A. Morales , Thang Q. Nguyen , Mark A. Banse
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0683 , G06F12/0831 , G06F12/0835 , G06F2212/1016
摘要： Piggy-back snoops are used for non-coherent memory transactions in distributed processing systems. Coherent and non-coherent memory transactions are received from a plurality of processing cores within a distributed processing system. Non-coherent snoop information for the non-coherent memory transactions is combined with coherent snoop information for the coherent memory transactions to form expanded snoop messages. The expanded snoop messages are then output to a snoop bus interconnect during snoop cycles for the distributed processing system. As such, when the processing cores monitor the snoop bus interconnect, the processing cores receive the non-coherent snoop information along with coherent snoop information within the same snoop cycle. While this piggy-backing of non-coherent snoop information with coherent snoop information uses an expanded snoop bus interconnect, usage of the coherent snoop bandwidth is significantly reduced thereby improving overall performance of the distributed processing system.
摘要翻译：捎带窥探用于分布式处理系统中的非相干内存事务。从分布式处理系统内的多个处理核心接收相干和非相干存储器事务。用于非相干存储器事务的非相干窥探信息与用于相干存储器事务的相干窥探信息组合以形成扩展的窥探消息。然后，在分布式处理系统的窥探周期中，扩展的窥探消息被输出到窥探总线互连。因此，当处理核心监视窥探总线互连时，处理核心在相同的窥探周期内接收非相干窥探信息以及连贯窥探信息。虽然具有相干窥探信息的非相干窥探信息的这种捎带使用扩展的窥探总线互连，但是相干窥探带宽的使用显着减少，从而提高了分布式处理系统的整体性能。

3. 发明授权

US09448741B2 Piggy-back snoops for non-coherent memory transactions within distributed processing systems 有权
标题翻译：对分布式处理系统内非相干内存事务的回拨监听
公开(公告)号：US09448741B2
公开(公告)日：2016-09-20
申请号：US14495209
申请日：2014-09-24
申请人： Sanjay R. Deshpande , John E. Larson , Fernando A. Morales , Thang Q. Nguyen , Mark A. Banse
发明人： Sanjay R. Deshpande , John E. Larson , Fernando A. Morales , Thang Q. Nguyen , Mark A. Banse
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0683 , G06F12/0831 , G06F12/0835 , G06F2212/1016
摘要： Piggy-back snoops are used for non-coherent memory transactions in distributed processing systems. Coherent and non-coherent memory transactions are received from a plurality of processing cores within a distributed processing system. Non-coherent snoop information for the non-coherent memory transactions is combined with coherent snoop information for the coherent memory transactions to form expanded snoop messages. The expanded snoop messages are then output to a snoop bus interconnect during snoop cycles for the distributed processing system. As such, when the processing cores monitor the snoop bus interconnect, the processing cores receive the non-coherent snoop information along with coherent snoop information within the same snoop cycle. While this piggy-backing of non-coherent snoop information with coherent snoop information uses an expanded snoop bus interconnect, usage of the coherent snoop bandwidth is significantly reduced thereby improving overall performance of the distributed processing system.
摘要翻译：捎带窥探用于分布式处理系统中的非相干内存事务。从分布式处理系统内的多个处理核心接收相干和非相干存储器事务。用于非相干存储器事务的非相干窥探信息与用于相干存储器事务的相干窥探信息组合以形成扩展的窥探消息。然后，在分布式处理系统的窥探周期中，扩展的窥探消息被输出到窥探总线互连。因此，当处理核心监视窥探总线互连时，处理核心在相同的窥探周期内接收非相干窥探信息以及连贯窥探信息。虽然具有相干窥探信息的非相干窥探信息的这种捎带使用扩展的窥探总线互连，但是相干窥探带宽的使用显着减少，从而提高了分布式处理系统的整体性能。

4. 发明申请

US20160085706A1 Methods And Systems For Controlling Ordered Write Transactions To Multiple Devices Using Switch Point Networks 有权
标题翻译：使用交换点网络控制多个设备的有序写入事务的方法和系统
公开(公告)号：US20160085706A1
公开(公告)日：2016-03-24
申请号：US14495096
申请日：2014-09-24
申请人： Sanjay R. Deshpande , Mark A. Banse , John E. Larson , Fernando A. Morales , Thang Q. Nguyen
发明人： Sanjay R. Deshpande , Mark A. Banse , John E. Larson , Fernando A. Morales , Thang Q. Nguyen
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F13/1621
摘要： Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.
摘要翻译：使用切换点网络控制从请求者设备到多个目标设备的有序写入事务。用于写事务的请求者设备和多个目标设备被耦合到互连交换点的网络。为与要写入的数据块相关联的多个宗地生成写入请求。写请求具有与要写入宗地的顺序相关联的特定顺序，并且这些写请求以特定顺序提供给交换点互连网络。然后至少一个切换点用于控制对多个目标设备的写入请求的流程，使得保持特定的顺序。在一个实施例中，目标设备是存储设备，并且特定顺序基于AXI（高级可扩展接口）协议。

5. 发明授权

US09026742B2 System and method for processing potentially self-inconsistent memory transactions 有权
标题翻译：用于处理可能自不一致内存事务的系统和方法
公开(公告)号：US09026742B2
公开(公告)日：2015-05-05
申请号：US11962331
申请日：2007-12-21
申请人： Sanjay R. Deshpande , Klas M. Bruce , Michael D. Snyder
发明人： Sanjay R. Deshpande , Klas M. Bruce , Michael D. Snyder
IPC分类号： G06F13/20 , G06F12/08
CPC分类号： G06F12/0828 , G06F12/0831 , G06F2212/1016 , G06F2212/507
摘要： A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state.
摘要翻译：处理器为与存储器请求相关联的一致性粒子提供存储器请求和一致性状态值。所述处理器还根据所述一致性状态值是否表示所述处理器的多个高速缓存的累积一致性状态，还提供第一指示符或第二指示符。第一指示符和第二指示符分别表示相关性状态值，表示累积相关性状态或潜在的非累积一致性状态。如果提供了第二指示符，则事务管理模块响应于接收到第二指示符来确定是否请求相关性颗粒的累积一致性状态。响应于确定请求累积一致性状态，事务管理模块向处理器提供对累积一致性状态的请求的指示符。否则，事务管理模块处理存储器事务而不请求累积一致性状态。

6. 发明授权

US07941499B2 Interprocessor message transmission via coherency-based interconnect 有权
标题翻译：通过基于相干性互连的处理器间消息传输
公开(公告)号：US07941499B2
公开(公告)日：2011-05-10
申请号：US11682867
申请日：2007-03-06
申请人： Becky G. Bruce , Sanjay R. Deshpande , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
发明人： Becky G. Bruce , Sanjay R. Deshpande , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
IPC分类号： G06F15/167
CPC分类号： G06F15/16 , G06F9/546 , G06F12/0833
摘要： A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要翻译：一种方法包括经由一致性互连在多处理器系统的处理器之间传送第一消息，由此第一消息包括一致性信息。该方法还包括经由一致性互连在多处理器系统的处理器之间传送第二消息，由此第二消息包括处理器内消息信息。系统包括一致性互连和处理器。处理器包括被配置为从一致性互连接收消息的接口，每个消息包括一致性信息或处理器间消息信息之一。该处理器还包括一个相关性管理模块，被配置为处理从至少一个消息获得的一致性信息，以及中断控制器，该中断控制器被配置为基于从至少一个消息获得的处理器间消息信息来生成中断。

7. 发明授权

US07502893B2 System and method for reporting cache coherency state retained within a cache hierarchy of a processing node 有权
标题翻译：用于报告高速缓存一致性状态的系统和方法保留在处理节点的高速缓存层级内
公开(公告)号：US07502893B2
公开(公告)日：2009-03-10
申请号：US11553146
申请日：2006-10-26
申请人： Sanjay R. Deshpande
发明人： Sanjay R. Deshpande
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A coherency state of a coherency granule is determined for each of a plurality of caches of a processor of a multiple-processor system to generate a plurality of coherency states in response to receiving a memory transaction request associated with the coherency granule at the processor. A coherency state of the coherency granule retained at the processor subsequent to the memory transaction request is determined based on the plurality of coherency states and an indicator representative of the coherency state of the coherency granule retained at the processor is provided for receipt by a cache coherency directory.
摘要翻译：针对多处理器系统的处理器的多个高速缓存中的每一个确定相关性颗粒的相关性状态，以响应于接收到处理器处的与相关性颗粒相关联的存储器事务请求来产生多个相关性状态。基于多个相关性状态来确定保留在存储器事务请求之后的处理器处的相干性颗粒的一致性状态，并且提供表示在处理器处保留的一致性颗粒的一致性状态的指示符以由高速缓存一致性接收目录。

8. 发明申请

US20090019232A1 SPECIFICATION OF COHERENCE DOMAIN DURING ADDRESS TRANSLATION 审中-公开
标题翻译：地址转换期间的协调域规范
公开(公告)号：US20090019232A1
公开(公告)日：2009-01-15
申请号：US11776267
申请日：2007-07-11
申请人： Sanjay R. Deshpande , Bryan D. Marietta , Michael D. Snyder , Gary L. Whisenhunt
发明人： Sanjay R. Deshpande , Bryan D. Marietta , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F12/08
CPC分类号： G06F12/1045 , G06F12/0813 , G06F12/0831
摘要： A processing system includes a plurality of coherency domains and a plurality of coherency agents. Each coherency agent is associated with at least one of the plurality of coherency domains. At a select coherency agent of the plurality of coherency agents, an address translation for a coherency message is performed using a first memory address to generate a second memory address. A select coherency domain of the plurality of coherency domains associated with the coherency message is determined at the select coherency agent based on the address translation. The coherency message and a coherency domain identifier of the select coherency domain are provided by the select coherency agent to a coherency interconnect for distribution to at least one of the plurality of coherency agents based on the coherency domain identifier.
摘要翻译：处理系统包括多个相干域和多个相干性代理。每个相关性代理与多个相关域中的至少一个相关联。在多个相关性代理的选择一致性代理处，使用第一存储器地址来执行一致性消息的地址转换以产生第二存储器地址。基于地址转换，在选择一致性代理处确定与相关性消息相关联的多个相关性域的选择一致性域。选择一致性域的一致性消息和一致性域标识符由选择一致性代理提供给一致性互连，用于基于相干域标识符分发给多个相关性代理中的至少一个。

9. 发明申请

US20080104330A1 SYSTEM AND METHOD FOR REPORTING CACHE COHERENCY STATE RETAINED WITHIN A CACHE HIERARCHY OF A PROCESSING NODE 有权
标题翻译：用于报告在加速节点的高速缓存中保留的缓存状态的系统和方法
公开(公告)号：US20080104330A1
公开(公告)日：2008-05-01
申请号：US11553146
申请日：2006-10-26
申请人： Sanjay R. Deshpande
发明人： Sanjay R. Deshpande
IPC分类号： G06F13/28
CPC分类号： G06F12/0817
摘要： A coherency state of a coherency granule is determined for each of a plurality of caches of a processor of a multiple-processor system to generate a plurality of coherency states in response to receiving a memory transaction request associated with the coherency granule at the processor. A coherency state of the coherency granule retained at the processor subsequent to the memory transaction request is determined based on the plurality of coherency states and an indicator representative of the coherency state of the coherency granule retained at the processor is provided for receipt by a cache coherency directory.
摘要翻译：针对多处理器系统的处理器的多个高速缓存中的每一个确定相关性颗粒的相关性状态，以响应于接收到处理器处的与相关性颗粒相关联的存储器事务请求来产生多个相关性状态。基于多个相关性状态来确定保留在存储器事务请求之后的处理器处的相干性颗粒的一致性状态，并且提供表示在处理器处保留的一致性颗粒的一致性状态的指示符以由高速缓存一致性接收目录。

10. 发明申请

US20090164737A1 SYSTEM AND METHOD FOR PROCESSING POTENTIALLY SELF-INCONSISTENT MEMORY TRANSACTIONS 有权
标题翻译：用于处理潜在的自发存储器交易的系统和方法
公开(公告)号：US20090164737A1
公开(公告)日：2009-06-25
申请号：US11962331
申请日：2007-12-21
申请人： Sanjay R. Deshpande , Klas M. Bruce , Michael D. Snyder
发明人： Sanjay R. Deshpande , Klas M. Bruce , Michael D. Snyder
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F12/0831 , G06F2212/1016 , G06F2212/507
摘要： A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state.
摘要翻译：处理器为与存储器请求相关联的一致性粒子提供存储器请求和一致性状态值。处理器还根据一致性状态值是否表示处理器的多个高速缓存的累积一致性状态来进一步提供第一指示符或第二指示符。第一指示符和第二指示符分别表示相关性状态值，表示累积相关性状态或潜在的非累积一致性状态。如果提供了第二指示符，则事务管理模块响应于接收到第二指示符来确定是否请求相关性颗粒的累积一致性状态。响应于确定请求累积一致性状态，事务管理模块向处理器提供对累积一致性状态的请求的指示符。否则，事务管理模块处理存储器事务而不请求累积一致性状态。

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