专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09397672B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09397672B2
公开(公告)日：2016-07-19
申请号：US13232368
申请日：2011-09-14
申请人： Seok-Bo Shim , Seok-Cheol Yoon
发明人： Seok-Bo Shim , Seok-Cheol Yoon
IPC分类号： H05K7/00 , H03L7/081 , G11C5/02 , G11C5/06 , G11C29/02 , H01L25/065 , H01L21/66 , H01L23/00
CPC分类号： H01L25/0657 , G11C5/025 , G11C5/063 , G11C29/023 , G11C29/025 , G11C29/028 , H01L22/32 , H01L22/34 , H01L23/49838 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06565 , H01L2225/06596 , H01L2924/00014 , H01L2924/1436 , H01L2924/15311 , H01L2924/3011 , H03L7/08 , H03L7/0816 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.
摘要翻译：半导体器件包括：封装基板，其具有设置在其第一表面上的多个外部连接端子和设置在其第二表面上的多个内部连接端子，并且与相应的一个外部连接端子电连接;第一半导体芯片堆叠并且具有用于提供第一信息的第一标记焊盘和用于响应于从第一标志焊盘提供的第一信息通过第一校正值调整参数的第一内部电路，以及第二半导体芯片堆叠在第一半导体芯片上并且具有用于提供第二信息的第二标志焊盘和用于响应于从第二标记焊盘提供的第二信息通过第二校正值来调整参数的第二内部电路。

2. 发明申请

US20100329050A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100329050A1
公开(公告)日：2010-12-30
申请号：US12876690
申请日：2010-09-07
申请人： Kyung-Whan KIM , Seok-Cheol Yoon
发明人： Kyung-Whan KIM , Seok-Cheol Yoon
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1093 , G11C7/1096 , G11C11/4076 , G11C11/4096 , G11C2207/002
摘要： A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.
摘要翻译：具有读和写操作的半导体存储器件包括：识别信号产生单元，用于在写操作期间产生鉴别信号; 以及选择延迟单元，用于响应于所述鉴别信号接收和选择性地延迟命令组信号。

3. 发明授权

US07821846B2 Semiconductor memory device and its driving method 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07821846B2
公开(公告)日：2010-10-26
申请号：US12240459
申请日：2008-09-29
申请人： Seok-Cheol Yoon
发明人： Seok-Cheol Yoon
IPC分类号： G11C7/10
CPC分类号： G11C7/1045
摘要： A semiconductor memory device including a first latch that latches a Mode Register Set (MRS) code consisting of multiple bits in response to an MRS command pulse, a code controller that generates a control signal in response to a code value of preset bits out of an output signal from the first latch, a second latch that selectively latches the output signal from the first latch in response to the control signal and a mode decoder that decodes an output signal from the second latch to output an operation mode.
摘要翻译：一种半导体存储器件，包括：第一锁存器，其响应于MRS指令脉冲锁存由多个位组成的模式寄存器组（MRS）代码;代码控制器，其响应于预定位的代码值而生成控制信号来自第一锁存器的输出信号;响应于控制信号选择性地锁存来自第一锁存器的输出信号的第二锁存器;以及解码来自第二锁存器的输出信号以输出操作模式的模式解码器。

4. 发明授权

US07619946B2 Active driver for use in semiconductor device 有权
标题翻译：用于半导体器件的主动驱动器
公开(公告)号：US07619946B2
公开(公告)日：2009-11-17
申请号：US11823695
申请日：2007-06-28
申请人： Sang-Jin Byeon , Seok-Cheol Yoon
发明人： Sang-Jin Byeon , Seok-Cheol Yoon
IPC分类号： G11C7/00
CPC分类号： G05F1/46
摘要： An active driver includes an internal voltage supply node, an internal voltage generator, and a test internal voltage driving circuit. The internal voltage generator generates an internal voltage having a first potential level in a normal operation to provide the internal voltage to the internal voltage supply node. The test internal voltage driving circuit drives an external voltage having a second potential level higher than the first potential level to the internal voltage supply node in a test operation.
摘要翻译：有源驱动器包括内部电压供应节点，内部电压发生器和测试内部电压驱动电路。内部电压发生器在正常操作中产生具有第一电位电平的内部电压，以向内部电压供应节点提供内部电压。测试内部电压驱动电路在测试操作中将具有高于第一电位电平的第二电位电平的外部电压驱动到内部电压供应节点。

5. 发明申请

US20090273364A1 CALIBRATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE CALIBRATION CIRCUIT 有权
标题翻译：校准电路，包括其的半导体存储器件以及校准电路的操作方法
公开(公告)号：US20090273364A1
公开(公告)日：2009-11-05
申请号：US12165110
申请日：2008-06-30
申请人： Chun-Seok Jeong , Seok-Cheol Yoon
发明人： Chun-Seok Jeong , Seok-Cheol Yoon
IPC分类号： H03K17/16
CPC分类号： H03K19/0016 , G11C7/1051 , G11C7/1057 , G11C2207/2254 , H03K19/0005
摘要： Calibration circuit, semiconductor memory device including the same, and operation method of the calibration circuit includes a calibration unit configured to generate a calibration code for controlling a termination resistance value, a calibration control unit configured to count a clock and allow the calibration unit to be enabled during a predetermined clock and a clock control unit configured to selectively supply the clock to the calibration control unit according to an operation mode of a semiconductor device employing the calibration circuit.
摘要翻译：校准电路，包括其的半导体存储器件和校准电路的操作方法包括：校准单元，被配置为生成用于控制终端电阻值的校准代码;校准控制单元，被配置为对时钟进行计数，并允许校准单元为在预定时钟期间使能;以及时钟控制单元，被配置为根据采用校准电路的半导体器件的操作模式，有选择地将时钟提供给校准控制单元。

6. 发明申请

US20090059681A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090059681A1
公开(公告)日：2009-03-05
申请号：US12165118
申请日：2008-06-30
申请人： Jae-Boum PARK , Seok-Cheol Yoon
发明人： Jae-Boum PARK , Seok-Cheol Yoon
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C5/147 , G11C5/143
摘要： Semiconductor memory device includes a detection circuit configured to detect a voltage level of an external power supply voltage and a core voltage generation circuit configured to vary a voltage level of the core voltage according to an output signal of the detection circuit to generate a uniform core voltage.
摘要翻译：半导体存储器件包括：检测电路，其被配置为检测外部电源电压的电压电平;以及核心电压产生电路，其被配置为根据检测电路的输出信号改变电压的电压电平，以产生均匀的核心电压。

7. 发明申请

US20080062798A1 Refresh operation of memory device 失效
标题翻译：刷新操作的内存设备
公开(公告)号：US20080062798A1
公开(公告)日：2008-03-13
申请号：US11819808
申请日：2007-06-29
申请人： Ki-Ho Kim , Seok-Cheol Yoon
发明人： Ki-Ho Kim , Seok-Cheol Yoon
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/20 , G11C11/4072
摘要： A memory device includes a refresh generator and a refresh command generation circuit. The refresh generator generates a refresh signal for a refresh operation enable. The refresh command generation circuit logically combines the refresh signal and a reset signal to produce a refresh command. The refresh command generation circuit produces the refresh command only when either the refresh signal or the reset signal is enabled.
摘要翻译：存储器件包括刷新发生器和刷新命令生成电路。刷新发生器产生用于刷新操作使能的刷新信号。刷新命令生成电路逻辑地组合刷新信号和复位信号以产生刷新命令。只有当刷新信号或复位信号被使能时，刷新命令产生电路才产生刷新命令。

8. 发明申请

US20080012629A1 Active driver for use in semiconductor device 有权
标题翻译：用于半导体器件的主动驱动器
公开(公告)号：US20080012629A1
公开(公告)日：2008-01-17
申请号：US11823695
申请日：2007-06-28
申请人： Sang-Jin Byeon , Seok-Cheol Yoon
发明人： Sang-Jin Byeon , Seok-Cheol Yoon
IPC分类号： G05F1/10
CPC分类号： G05F1/46
摘要： An active driver includes an internal voltage supply node, an internal voltage generator, and a test internal voltage driving circuit. The internal voltage generator generates an internal voltage having a first potential level in a normal operation to provide the internal voltage to the internal voltage supply node. The test internal voltage driving circuit drives an external voltage having a second potential level higher than the first potential level to the internal voltage supply node in a test operation.
摘要翻译：有源驱动器包括内部电压供应节点，内部电压发生器和测试内部电压驱动电路。内部电压发生器在正常操作中产生具有第一电位电平的内部电压，以向内部电压供应节点提供内部电压。测试内部电压驱动电路在测试操作中将具有高于第一电位电平的第二电位电平的外部电压驱动到内部电压供应节点。

9. 发明申请

US20070069783A1 Delay locked loop in synchronous semiconductor memory device and driving method thereof 有权
标题翻译：同步半导体存储器件中的延迟锁定环及其驱动方法
公开(公告)号：US20070069783A1
公开(公告)日：2007-03-29
申请号：US11528644
申请日：2006-09-28
申请人： Young-Jun Ku , Seok-Cheol Yoon
发明人： Young-Jun Ku , Seok-Cheol Yoon
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , G11C7/1072 , G11C7/222 , H03L7/0805
摘要： A semiconductor memory device including a delay locked loop can minimize current consumption during a precharge power down mode. The delay locked loop includes a buffer control block for generating a clock buffer enable signal in response to first and second signals, wherein the first signal represents a precharge power down mode and the second signal represents a reset of the delay locked loop, a clock buffering block, controlled by the clock buffer enable signal, for buffering an external clock to generate a reference clock, and a feedback loop for delaying the reference clock until a delay locking state to thereby output a DLL output clock.
摘要翻译：包括延迟锁定环路的半导体存储器件可以使预充电掉电模式期间的电流消耗最小化。延迟锁定环包括缓冲器控制块，用于响应于第一和第二信号产生时钟缓冲器使能信号，其中第一信号表示预充电掉电模式，第二信号表示延迟锁定环的复位，时钟缓冲由时钟缓冲器使能信号控制，用于缓冲外部时钟以产生参考时钟，以及用于延迟参考时钟直到延迟锁定状态从而输出DLL输出时钟的反馈回路。

10. 发明授权

US07031202B2 Method and apparatus for rapidly storing data in memory cell without voltage loss 失效
标题翻译：用于在没有电压损失的情况下将数据快速存储在存储单元中的方法和装置
公开(公告)号：US07031202B2
公开(公告)日：2006-04-18
申请号：US10744257
申请日：2003-12-22
申请人： Seok-Cheol Yoon , Jae-Jin Lee
发明人： Seok-Cheol Yoon , Jae-Jin Lee
IPC分类号： G11C11/34
CPC分类号： G11C11/4085 , G11C8/08 , G11C11/406 , G11C2211/4068
摘要： The present relates to a memory device; and, more particularly, to an apparatus and a method for preventing a loss of reliability of data, which are stored in memory cell, at the time of restoring and writing the data. The semiconductor memory device according to the present invention comprises: a high voltage generator for boosting an external voltage level and then for producing a first high voltage level; a pumping control signal generator for issuing a pumping control signal, which is activated in a restore section and a write section, in response to a command signal; a pumping unit for outputting the first high voltage level from the high voltage generator or for boosting the high voltage level in order to generate a second high voltage plus level in response to the pumping control signal from the pumping control signal generator, wherein the second high voltage plus level is higher than the first high voltage level; and a word line driver for driving the word line WL using the first high voltage level and for driving the word line WL using the second high voltage plus level from the pumping unit in the restore and write sections.
摘要翻译：本发明涉及一种存储装置; 更具体地，涉及在恢复和写入数据时防止存储在存储单元中的数据的可靠性损失的装置和方法。根据本发明的半导体存储器件包括：高压发生器，用于升高外部电压电平，然后产生第一高电压电平; 泵送控制信号发生器，用于响应于命令信号发出在恢复部分和写入部分中激活的泵送控制信号; 泵送单元，用于从高压发生器输出第一高电压电平或用于升高高电压电平，以便响应于来自泵送控制信号发生器的泵送控制信号产生第二高电压加电平，其中第二高电平电压加电平高于第一高电压电平; 以及字线驱动器，用于使用第一高电压电平驱动字线WL，并且使用来自恢复和写入部分中的泵送单元的第二高电压加电平来驱动字线WL。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式