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1. 发明授权

US09397672B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09397672B2
公开(公告)日：2016-07-19
申请号：US13232368
申请日：2011-09-14
申请人： Seok-Bo Shim , Seok-Cheol Yoon
发明人： Seok-Bo Shim , Seok-Cheol Yoon
IPC分类号： H05K7/00 , H03L7/081 , G11C5/02 , G11C5/06 , G11C29/02 , H01L25/065 , H01L21/66 , H01L23/00
CPC分类号： H01L25/0657 , G11C5/025 , G11C5/063 , G11C29/023 , G11C29/025 , G11C29/028 , H01L22/32 , H01L22/34 , H01L23/49838 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06565 , H01L2225/06596 , H01L2924/00014 , H01L2924/1436 , H01L2924/15311 , H01L2924/3011 , H03L7/08 , H03L7/0816 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.
摘要翻译：半导体器件包括：封装基板，其具有设置在其第一表面上的多个外部连接端子和设置在其第二表面上的多个内部连接端子，并且与相应的一个外部连接端子电连接;第一半导体芯片堆叠并且具有用于提供第一信息的第一标记焊盘和用于响应于从第一标志焊盘提供的第一信息通过第一校正值调整参数的第一内部电路，以及第二半导体芯片堆叠在第一半导体芯片上并且具有用于提供第二信息的第二标志焊盘和用于响应于从第二标记焊盘提供的第二信息通过第二校正值来调整参数的第二内部电路。

2. 发明申请

US20120200329A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120200329A1
公开(公告)日：2012-08-09
申请号：US13232368
申请日：2011-09-14
申请人： Seok-Bo SHIM , Seok-Cheol Yoon
发明人： Seok-Bo SHIM , Seok-Cheol Yoon
IPC分类号： H01L23/48 , H01L23/488 , H03L7/06
CPC分类号： H01L25/0657 , G11C5/025 , G11C5/063 , G11C29/023 , G11C29/025 , G11C29/028 , H01L22/32 , H01L22/34 , H01L23/49838 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/0651 , H01L2225/06565 , H01L2225/06596 , H01L2924/00014 , H01L2924/1436 , H01L2924/15311 , H01L2924/3011 , H03L7/08 , H03L7/0816 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.
摘要翻译：半导体器件包括：封装基板，其具有设置在其第一表面上的多个外部连接端子和设置在其第二表面上的多个内部连接端子，并且与相应的一个外部连接端子电连接;第一半导体芯片堆叠并且具有用于提供第一信息的第一标记焊盘和用于响应于从第一标志焊盘提供的第一信息通过第一校正值调整参数的第一内部电路，以及第二半导体芯片堆叠在第一半导体芯片上并且具有用于提供第二信息的第二标志焊盘和用于响应于从第二标记焊盘提供的第二信息通过第二校正值来调整参数的第二内部电路。

3. 发明授权

US08159898B2 Architecture of highly integrated semiconductor memory device 有权
标题翻译：高度集成的半导体存储器件的架构
公开(公告)号：US08159898B2
公开(公告)日：2012-04-17
申请号：US12346311
申请日：2008-12-30
申请人： Seok-Cheol Yoon
发明人： Seok-Cheol Yoon
IPC分类号： G11C8/00
CPC分类号： G11C5/025
摘要： A semiconductor memory device includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region corresponding to the first memory bank; a second row control circuit region corresponding to a second memory bank and disposed adjacent to the first row control circuit region; and a second column control circuit region corresponding to a third memory bank and disposed adjacent to the first column control circuit region.
摘要翻译：半导体存储器件包括：对应于第一存储体的第一行控制电路区域; 对应于第一存储体的第一列控制电路区域; 对应于第二存储体并与第一行控制电路区相邻设置的第二行控制电路区; 以及对应于第三存储体并且与第一列控制电路区域相邻设置的第二列控制电路区域。

4. 发明授权

US07668032B2 Refresh operation of memory device 失效
标题翻译：刷新操作的内存设备
公开(公告)号：US07668032B2
公开(公告)日：2010-02-23
申请号：US11819808
申请日：2007-06-29
申请人： Ki-Ho Kim , Seok-Cheol Yoon
发明人： Ki-Ho Kim , Seok-Cheol Yoon
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C11/406 , G11C7/20 , G11C11/4072
摘要： A memory device includes a refresh generator and a refresh command generation circuit. The refresh generator generates a refresh signal for a refresh operation enable. The refresh command generation circuit logically combines the refresh signal and a reset signal to produce a refresh command. The refresh command generation circuit produces the refresh command only when either the refresh signal or the reset signal is enabled.
摘要翻译：存储器件包括刷新发生器和刷新命令生成电路。刷新发生器产生用于刷新操作使能的刷新信号。刷新命令生成电路逻辑地组合刷新信号和复位信号以产生刷新命令。只有当刷新信号或复位信号被使能时，刷新命令产生电路才产生刷新命令。

5. 发明申请

US20090323451A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20090323451A1
公开(公告)日：2009-12-31
申请号：US12323221
申请日：2008-11-25
申请人： Kang-Seol LEE , Seok-Cheol Yoon
发明人： Kang-Seol LEE , Seok-Cheol Yoon
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/14 , G11C5/063
摘要： A semiconductor memory device that prevents a power noise generated at a data input/output pad in a read operation from affecting a data strobe signal pad. The semiconductor memory device includes first power supply voltage pads for a data output circuit, a first power mesh, and a second power supply voltage pad for a data strobe signal output circuit. The first power mesh connects first power supply voltage pads to one another. The second power supply voltage pad is electrically separated from the first power mesh.
摘要翻译：一种半导体存储器件，其防止在读取操作中在数据输入/输出焊盘处产生的功率噪声影响数据选通信号焊盘。半导体存储器件包括用于数据输出电路的第一电源电压焊盘，第一电源网和用于数据选通信号输出电路的第二电源电压焊盘。第一个电源网将第一个电源电压焊盘彼此连接。第二电源电压焊盘与第一电源网电隔离。

6. 发明授权

US07106640B2 Semiconductor memory device capable of detecting repair address at high speed 有权
标题翻译：能够高速检测修复地址的半导体存储器件
公开(公告)号：US07106640B2
公开(公告)日：2006-09-12
申请号：US11024902
申请日：2004-12-30
申请人： Seok-Cheol Yoon , Jae-Jin Lee
发明人： Seok-Cheol Yoon , Jae-Jin Lee
IPC分类号： G11C7/00
CPC分类号： G11C29/027 , G11C29/24 , G11C29/781 , G11C2029/4402
摘要： There is provided a semiconductor memory device capable of detecting a repaired address in a test mode. The semiconductor memory device includes: a plurality of unit address detectors for comparing 1-bit address signal with a stored 1-bit repair address signal to output a repair signal, and for buffering the stored repair address signal and outputting the buffered repair address signal as the repair signal in a test mode; a redundancy address detector for combining the plurality of repair signals from the unit address detectors and outputting a detection signal for detecting whether a current input address is a redundancy address; and a redundancy flag signal generator for generating a redundancy flag signal in response to the detection signal and transferring the redundancy flag signal to a data output path.
摘要翻译：提供了能够在测试模式下检测修复的地址的半导体存储器件。半导体存储器件包括：多个单元地址检测器，用于将1位地址信号与存储的1位修复地址信号进行比较，以输出修复信号，并用于缓存存储的修复地址信号，并将缓冲的修复地址信号作为修复信号处于测试模式; 冗余地址检测器，用于组合来自单元地址检测器的多个修复信号，并输出用于检测当前输入地址是否为冗余地址的检测信号; 以及冗余标志信号发生器，用于响应于检测信号产生冗余标志信号，并将冗余标志信号传送到数据输出路径。

7. 发明授权

US08970236B2 Internal voltage generating circuit for preventing voltage drop of internal voltage 有权
标题翻译：用于防止内部电压降低的内部电压产生电路
公开(公告)号：US08970236B2
公开(公告)日：2015-03-03
申请号：US13154680
申请日：2011-06-07
申请人： kang-Seol Lee , Seok-Cheol Yoon
发明人： kang-Seol Lee , Seok-Cheol Yoon
IPC分类号： G01R31/00 , G01R31/02 , G05F1/46 , G11C5/14 , G11C29/06 , G11C29/12
CPC分类号： G05F1/465 , G11C5/147 , G11C29/06 , G11C29/12005
摘要： An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.
摘要翻译：内部电压产生电路用于对半导体器件执行TDBI（老化测试）操作。内部电压产生电路在测试操作中响应于激活的测试操作信号，在不仅备用部分而且在有效部分中产生作为内部电压的高电压电平的内部电压。因此，防止了测试操作的待机部分中的内部电压的下降以及由于开路或短路引起的故障。结果，确保了通过防止由内部电路的击穿引起的闩锁而产生的半导体芯片的可靠性。

8. 发明授权

US08248126B2 Clock control circuit and data alignment circuit including the same 有权
标题翻译：时钟控制电路和数据对准电路包括它们
公开(公告)号：US08248126B2
公开(公告)日：2012-08-21
申请号：US12006113
申请日：2007-12-31
申请人： Ji-Eun Jang , Seok-Cheol Yoon
发明人： Ji-Eun Jang , Seok-Cheol Yoon
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222
摘要： A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal.
摘要翻译：时钟控制电路可以防止当上升的选通信号和下降的选通信号在脉冲宽度上变化并因此彼此重叠时发生的故障。时钟控制电路包括：第一时钟控制单元，被配置为接收上升选通信号和下降选通信号，并输出调节后的上升选通信号，其使能脉冲宽度不与下降选通信号的使能脉冲宽度重叠。

9. 发明申请

US20110234288A1 INTERNAL VOLTAGE GENERATING CIRCUIT FOR PREVENTING VOLTAGE DROP OF INTERNAL VOLTAGE 审中-公开
标题翻译：内部电压发生电路，用于防止内部电压降低
公开(公告)号：US20110234288A1
公开(公告)日：2011-09-29
申请号：US13154680
申请日：2011-06-07
申请人： Kang-Seol LEE , Seok-Cheol Yoon
发明人： Kang-Seol LEE , Seok-Cheol Yoon
IPC分类号： H03L5/00
CPC分类号： G05F1/465 , G11C5/147 , G11C29/06 , G11C29/12005
摘要： An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.
摘要翻译：内部电压产生电路用于对半导体器件执行TDBI（老化测试）操作。内部电压产生电路在测试操作中响应于激活的测试操作信号，在不仅备用部分而且在有效部分中产生作为内部电压的高电压电平的内部电压。因此，防止了测试操作的待机部分中的内部电压的下降以及由于开路或短路引起的故障。结果，确保了通过防止由内部电路的击穿引起的闩锁而产生的半导体芯片的可靠性。

10. 发明授权

US07813211B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07813211B2
公开(公告)日：2010-10-12
申请号：US11956822
申请日：2007-12-14
申请人： Kyung-Whan Kim , Seok-Cheol Yoon
发明人： Kyung-Whan Kim , Seok-Cheol Yoon
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/1093 , G11C7/1096 , G11C11/4076 , G11C11/4096 , G11C2207/002
摘要： A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.
摘要翻译：具有读和写操作的半导体存储器件包括：识别信号产生单元，用于在写操作期间产生鉴别信号; 以及选择延迟单元，用于响应于所述鉴别信号接收和选择性地延迟命令组信号。

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