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1. 发明授权

US09037929B2 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US09037929B2
公开(公告)日：2015-05-19
申请号：US13225621
申请日：2011-09-06
申请人： Jung Hwan Lee , Seong Je Park
发明人： Jung Hwan Lee , Seong Je Park
IPC分类号： G11C29/00 , G11C16/34 , G11C16/10 , G06F11/10 , G11C16/04
CPC分类号： G11C16/3459 , G06F11/1048 , G11C16/0483 , G11C16/10
摘要： A method of operating a semiconductor memory device according to an aspect of the present disclosure includes performing a program loop, including a program operation and a program verification operation, in order to store input data in selected memory cells, performing a first error bit check operation for comparing the number of error bits of data not identical with the input data, with the number of correctable error bits, if the number of error bits is equal to or smaller than the number of correctable error bits, performing a second error bit check operation for comparing the number of error bits with the reference number of bits for replacement determination, and if the number of error bits is greater than the reference number of bits for replacement determination, updating failed column address information by adding the column address of a memory cell, having the error bits, to the failed column address information.
摘要翻译：根据本公开的一个方面的操作半导体存储器件的方法包括执行包括程序操作和程序验证操作的程序循环，以便将输入数据存储在所选择的存储器单元中，执行第一错误位检查操作用于将与输入数据不同的数据的错误位的数量与可校正错误位的数量进行比较，如果错误位的数量等于或小于可校正错误位的数量，则执行第二错误位检查操作用于将错误位数与用于替换确定的参考比特数进行比较，并且如果错误位的数量大于用于替换确定的参考比特数，则通过将存储器单元的列地址相加来更新故障列地址信息具有错误位，失败的列地址信息。

2. 发明授权

US08867298B2 Semiconductor device and operating method thereof 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US08867298B2
公开(公告)日：2014-10-21
申请号：US13456965
申请日：2012-04-26
申请人： Seong Je Park
发明人： Seong Je Park
IPC分类号： G11C8/00 , G11C8/12 , G11C8/06 , G11C7/10 , G11C16/04
CPC分类号： G11C8/12 , G11C7/1051 , G11C7/12 , G11C7/18 , G11C8/06 , G11C16/0483 , G11C16/24
摘要： A semiconductor device includes a first bit line section coupled to a first cell string, a second bit line section coupled to a second cell string, a page buffer coupled to the first bit line section and a switching circuit formed between the first bit line section and the second bit line section, wherein the switching circuit couples the first bit line section to second bit line section in response to a select signal.
摘要翻译：半导体器件包括耦合到第一单元串的第一位线部分，耦合到第二单元串的第二位线部分，耦合到第一位线部分的页面缓冲器和形成在第一位线部分和第二位线部分，其中开关电路响应于选择信号将第一位线部分耦合到第二位线部分。

3. 发明授权

US08750048B2 Memory device and method for operating the same 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US08750048B2
公开(公告)日：2014-06-10
申请号：US13238435
申请日：2011-09-21
申请人： Myung Cho , Seong-Je Park , Jung-Hwan Lee , Ji-Hwan Kim , Beom-Seok Hah
发明人： Myung Cho , Seong-Je Park , Jung-Hwan Lee , Ji-Hwan Kim , Beom-Seok Hah
IPC分类号： G11C16/34 , G11C16/28 , G11C16/06 , G11C16/26
CPC分类号： G11C11/5642 , G11C16/0483 , G11C2211/5646
摘要： A memory includes at least one first flag cell configured to store first flag data, at least one second flag cell configured to store second flag data, at least one first sensing node having a voltage level determined by the first flag data of the first flag cell, at least one second sensing having a voltage level determined by the second flag data of the second flag cell, a selection circuit configured to select the first sensing node or the second sensing node in response to a flag address; and a determination circuit having an internal node through which current corresponding to a voltage level of a selected sensing node flows and configured to determine a logic value of flag data corresponding to the selected sensing node among the first and second flag data by using an amount of current flowing through the internal node.
摘要翻译：存储器包括被配置为存储第一标志数据的至少一个第一标志单元，被配置为存储第二标志数据的至少一个第二标志单元，具有由第一标志单元的第一标志数据确定的电压电平的至少一个第一感测节点至少一个第二感测具有由第二标志单元的第二标志数据确定的电压电平，选择电路被配置为响应于标志地址选择第一感测节点或第二感测节点; 以及确定电路，其具有内部节点，通过所述内部节点流过与所选择的感测节点的电压电平相对应的电流，并且被配置为通过使用一定数量的第一和第二标志数据来确定与所选择的感测节点对应的标志数据的逻辑值电流流过内部节点。

4. 发明授权

US08451665B2 Non-volatile memory device and method for operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US08451665B2
公开(公告)日：2013-05-28
申请号：US13232304
申请日：2011-09-14
申请人： Seong-Je Park , Jung-Hwan Lee , Ji-Hwan Kim , Myung Cho , Beom-Seok Hah
发明人： Seong-Je Park , Jung-Hwan Lee , Ji-Hwan Kim , Myung Cho , Beom-Seok Hah
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/16
摘要： A method for operating a non-volatile memory device includes selecting a word line of a plurality of word lines in response to a program command and an received address, determining whether the selected word line is a word line set among the word lines, performing an erase operation on a second word line group of the word lines in response to a result of the determining, and performing a program operation on the selected word line.
摘要翻译：用于操作非易失性存储器件的方法包括响应于程序命令和接收到的地址选择多个字线的字线，确定所选择的字线是否是字线中的字线，执行响应于所述确定的结果对所述字线的第二字线组进行擦除操作，以及对所选择的字线执行编程操作。

5. 发明申请

US20130033940A1 APPARATUS AND METHODS OF BIT LINE SETUP 有权
标题翻译：位线设置的装置和方法
公开(公告)号：US20130033940A1
公开(公告)日：2013-02-07
申请号：US13195548
申请日：2011-08-01
申请人： Myung Cho , Seong Je Park , Jung Hwan Lee
发明人： Myung Cho , Seong Je Park , Jung Hwan Lee
IPC分类号： G11C16/10 , G11C16/06
CPC分类号： G11C16/06 , G11C11/5628 , G11C16/26
摘要： Methods and apparatus are disclosed, including an apparatus that has a memory cell array with a memory cell selectively coupled to a bit line. A control circuit is configured to provide a control signal. A voltage generator is configured to provide a sense signal and a precharge signal in response to the control signal. The apparatus further includes a page buffer configured to provide a bit line voltage to the bit line based on the sense signal and the precharge signal, to thereby control a programming of the memory cell.
摘要翻译：公开了方法和装置，包括具有存储单元阵列的装置，存储单元阵列选择性地耦合到位线。控制电路被配置为提供控制信号。电压发生器被配置为响应于控制信号提供感测信号和预充电信号。该装置还包括一个页面缓冲器，其配置为基于感测信号和预充电信号向位线提供位线电压，从而控制存储单元的编程。

6. 发明申请

US20120275257A1 SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：半导体器件及其工作方法
公开(公告)号：US20120275257A1
公开(公告)日：2012-11-01
申请号：US13456965
申请日：2012-04-26
申请人： Seong Je PARK
发明人： Seong Je PARK
IPC分类号： G11C8/04 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1051 , G11C7/12 , G11C7/18 , G11C8/06 , G11C16/0483 , G11C16/24
摘要： A semiconductor device includes a first bit line section coupled to a first cell string, a second bit line section coupled to a second cell string, a page buffer coupled to the first bit line section and a switching circuit formed between the first bit line section and the second bit line section, wherein the switching circuit couples the first bit line section to second bit line section in response to a select signal.
摘要翻译：半导体器件包括耦合到第一单元串的第一位线部分，耦合到第二单元串的第二位线部分，耦合到第一位线部分的页面缓冲器和形成在第一位线部分和第二位线部分，其中开关电路响应于选择信号将第一位线部分耦合到第二位线部分。

7. 发明申请

US20120236618A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：半导体存储器件及其工作方法
公开(公告)号：US20120236618A1
公开(公告)日：2012-09-20
申请号：US13420038
申请日：2012-03-14
申请人： Jung Hwan LEE , Seong Je PARK , Ji Hwan KIM , Myung CHO , Beom Seok HAH
发明人： Jung Hwan LEE , Seong Je PARK , Ji Hwan KIM , Myung CHO , Beom Seok HAH
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C16/10
摘要： A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the CAM cells, perform a test operation for detecting unstable CAM cells in each of which a difference between a threshold voltage and the read voltage is smaller than a permitted limit, from among the CAM cells, and perform an erase operation or a program operation for the unstable CAM cells; and a controller configured to control the operation circuit so that the program operation for storing the setting data in the unstable CAM cells is performed if the number of unstable CAM cells detected in the test operation is greater than a permitted value.
摘要翻译：半导体存储器件包括：存储器阵列，被配置为包括用于存储输入数据的存储器单元和用于存储用于设置操作条件的设置数据的代码地址存储器（CAM）单元; 配置为通过向CAM单元提供读取电压来执行CAM读取操作的操作电路，执行用于检测阈值电压和读取电压之间的差小于允许极限的不稳定的CAM单元的测试操作，从CAM单元中进行擦除操作或对不稳定的CAM单元的编程动作; 以及控制器，其被配置为如果在测试操作中检测到的不稳定的CAM单元的数量大于允许值，则执行用于将设置数据存储在不稳定的CAM单元中的程序操作。

8. 发明授权

US08270215B2 Nonvolatile memory device and method of programming the same 失效
标题翻译：非易失存储器件及其编程方法
公开(公告)号：US08270215B2
公开(公告)日：2012-09-18
申请号：US12826064
申请日：2010-06-29
申请人： Byoung Sung You , Jin Su Park , Seong Je Park
发明人： Byoung Sung You , Jin Su Park , Seong Je Park
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C2216/14
摘要： In a nonvolatile memory device, a cache program operation for the next data is performed in a first latch, and a verification program operation for the current data is performed using a second latch. Thus, data collision can be avoided and execution time can be reduced.
摘要翻译：在非易失性存储器件中，在第一锁存器中执行用于下一数据的高速缓存程序操作，并且使用第二锁存器执行当前数据的验证程序操作。因此，可以避免数据冲突，并且可以减少执行时间。

9. 发明授权

US08238163B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08238163B2
公开(公告)日：2012-08-07
申请号：US12647571
申请日：2009-12-28
申请人： Seong Je Park
发明人： Seong Je Park
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： A page buffer of a nonvolatile memory device according to the present disclosure comprises a first data latch unit configured to store data for program or program inhibition, a second data latch unit configured to store data for setting threshold voltage states of cells to be programmed, and a 1-bit pass determination unit configured to determine whether a cell to be programmed has been programmed to exceed a verification voltage by grounding or making floating a first verification signal output terminal in response to data set to a first node of the first data latch unit and data applied to a sense node.
摘要翻译：根据本公开的非易失性存储器件的页缓冲器包括被配置为存储用于程序或程序禁止的数据的第一数据锁存单元，配置为存储用于设置要编程的单元的阈值电压状态的数据的第二数据锁存单元，以及 1位通过确定单元，被配置为响应于设置到第一数据锁存单元的第一节点的数据，通过接地或使浮动第一验证信号输出端子来确定要编程的单元是否已被编程为超过验证电压以及应用于感测节点的数据。

10. 发明申请

US20120057409A1 NONVOLATILE MEMORY DEVICE AND METHOD OF READING THE SAME 有权
标题翻译：非易失存储器件及其读取方法
公开(公告)号：US20120057409A1
公开(公告)日：2012-03-08
申请号：US13183675
申请日：2011-07-15
申请人： Jung Hwan LEE , Seong Je PARK
发明人： Jung Hwan LEE , Seong Je PARK
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/1048 , G11C7/12 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C2211/5634 , G11C2211/5642
摘要： A read method of a nonvolatile memory device according to an exemplary embodiment of this disclosure includes precharging bit lines coupled to memory cells, performing a first read operation by supplying a first reference voltage to the memory cells in order to determine the data stored in the memory cells, precharging bit lines coupled to undetermined memory cells whose data has not been determined by the first read operation, and performing a second read operation by supplying a second reference voltage to the memory cells in order to determine data stored in the undetermined memory cells.
摘要翻译：根据本公开的示例性实施例的非易失性存储器件的读取方法包括预先充电与存储器单元耦合的位线，通过向存储器单元提供第一参考电压来执行第一读取操作，以便确定存储在存储器中的数据单元，预充电位线，其耦合到其数据尚未被第一读取操作确定的未确定存储单元，以及通过向存储器单元提供第二参考电压来执行第二读取操作，以便确定存储在未确定的存储器单元中的数据。

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