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1. 发明授权

US07413129B2 USB device with secondary USB on-the-go function 有权
标题翻译：具有辅助USB即插即用功能的USB设备
公开(公告)号：US07413129B2
公开(公告)日：2008-08-19
申请号：US10954777
申请日：2004-09-30
申请人： Serge Fruhauf
发明人： Serge Fruhauf
IPC分类号： G06K19/06
CPC分类号： G06F13/385
摘要： A USB device includes first and second communications ports and a processor operable for configuring the first communications port for connecting to a USB host and configuring the second communications port as a USB master connecting to a USB slave device. The processor can be formed as a USB device controller operatively connected to the first communications port and USB On-The-Go device controller operatively connected to a second communications port for creating a point-to-point connection to the USB slave device.
摘要翻译： USB设备包括第一和第二通信端口以及可操作用于配置用于连接到USB主机的第一通信端口并将第二通信端口配置为连接到USB从设备的USB主机的处理器。处理器可以形成为可操作地连接到第一通信端口的USB设备控制器和可操作地连接到第二通信端口的USB On-The-Go设备控制器，用于创建到USB从设备的点对点连接。

2. 发明申请

US20070075746A1 System and method for glitch detection in a secure microcontroller 有权
标题翻译：安全微控制器中毛刺检测的系统和方法
公开(公告)号：US20070075746A1
公开(公告)日：2007-04-05
申请号：US11243328
申请日：2005-10-04
申请人： Serge Fruhauf , Alain Pomet
发明人： Serge Fruhauf , Alain Pomet
IPC分类号： H03K19/00
CPC分类号： G01R31/31719 , G06K19/07309
摘要： An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.
摘要翻译：一种装置包括由能够执行一个或多个功能的逻辑形成的多个宏小区。该装置还包括能够接收时钟信号并且向每个宏小区提供时钟信号的至少一个副本的时钟树。时钟树包括每个宏小区内的本地分支，其中每个本地分支能够提供时钟信号的至少一个副本。此外，该装置包括至少一个毛刺检测电路，能够检测由宏单元中的本地分支提供的时钟信号的一个或多个拷贝中的毛刺。

3. 发明授权

US07181649B2 Universal serial bus (USB) smart card having enhanced testing features and related system, integrated circuit, and methods 有权
标题翻译：通用串行总线（USB）智能卡具有增强的测试功能和相关系统，集成电路和方法
公开(公告)号：US07181649B2
公开(公告)日：2007-02-20
申请号：US10434820
申请日：2003-05-09
申请人： Serge Fruhauf , Taylor J. Leaming , Alain C. Pomet
发明人： Serge Fruhauf , Taylor J. Leaming , Alain C. Pomet
IPC分类号： G06F11/00
CPC分类号： G06K7/10465 , G06K7/0008 , G06K7/0095 , G06K19/07 , G06K19/07733
摘要： An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.
摘要翻译：用于智能卡的集成电路可以包括用于与USB主机设备通信的通用串行总线（USB）收发器和连接到USB收发器的微处理器，并且可以在测试模式和用户模式下操作。当处于测试模式时，微处理器可以经由至少一个USB收发器从USB主机设备接收至少一个测试供应商特定请求（VSR）来执行测试操作。作为示例，测试操作可以包括对微处理器的控制逻辑进行扫描测试，检测至少一个缓冲器的状态并将状态传送到USB主机设备，将测试数据写入至少一个指定的缓冲器，并将测试数据从所述至少一个指定的缓冲器到达所述USB主机设备，和/或以降低的功率运行。

4. 发明申请

US20060053244A1 Generic universal serial bus device operable at low and full speed and adapted for use in a smart card device 有权
标题翻译：通用通用串行总线设备，可以低速和全速工作，适用于智能卡设备
公开(公告)号：US20060053244A1
公开(公告)日：2006-03-09
申请号：US10937752
申请日：2004-09-09
申请人： Serge Fruhauf , Robert Leydier
发明人： Serge Fruhauf , Robert Leydier
IPC分类号： G06F13/20
CPC分类号： G06F13/4068
摘要： A USB device, integrated circuit, smart card and method are disclosed. A USB transceiver is connected to a data interface and operable at a respective low speed and full speed configuration. A processor as a USB device controller is operatively connected to the low speed USB transceiver and full speed USB transceiver and operable for transmitting a different device descriptor to a USB host for performing an enumeration depending on whether a low speed or high speed operation is chosen.
摘要翻译：公开了USB设备，集成电路，智能卡和方法。 USB收发器连接到数据接口并可在相应的低速和全速配置下操作。作为USB设备控制器的处理器可操作地连接到低速USB收发器和全速USB收发器，并且可操作用于根据是否选择低速或高速操作来向USB主机发送不同的设备描述符以执行枚举。

5. 发明授权

US5969403A Physical fuse for semiconductor integrated circuit 失效
标题翻译：物理保险丝用于半导体集成电路
公开(公告)号：US5969403A
公开(公告)日：1999-10-19
申请号：US678148
申请日：1996-07-11
申请人： Richard Pierre Fournel , Serge Fruhauf , Fran.cedilla.ois Tailliet
发明人： Richard Pierre Fournel , Serge Fruhauf , Fran.cedilla.ois Tailliet
IPC分类号： B42D15/10 , G06K19/07 , G06K19/077 , H01L21/82 , H01L27/02 , H01L29/00
CPC分类号： H01L27/0251 , H01L27/0248
摘要： A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a diffusion of metal up to the junction. This short-circuits the junction. The detection is done also by the forward biasing of the junction, but with a low current or a low voltage. The detection can also be done with reverse biasing.
摘要翻译：用于集成电路的熔断器由覆盖有金属接触的浅NP结构成，半导体区域不被过度掺杂。为了熔断熔断器，结点被正向偏置，其电流足以使金属扩散到结点。这会使接合点短路。该检测也通过结的正向偏置来实现，但是具有低电流或低电压。也可以通过反向偏置进行检测。

6. 发明授权

US4952796A Light detection circuit having a junction reverse-biased by a current generator 失效
标题翻译：具有由电流发生器反向偏置的结的光检测电路
公开(公告)号：US4952796A
公开(公告)日：1990-08-28
申请号：US235365
申请日：1988-08-23
申请人： Serge Fruhauf , Laurent Sourgen
发明人： Serge Fruhauf , Laurent Sourgen
IPC分类号： G01J1/02 , G06F12/14 , G06F21/06 , G06K19/07 , G06K19/073 , G06K19/10 , G07F7/10 , H01L27/144 , H01L31/02 , H01L31/10 , H03F3/08
CPC分类号： G07F7/1008 , G06K19/073 , G06K19/07372 , G06Q20/341 , G07F7/082 , H01L23/576 , H01L27/1443 , H01L31/02019 , H01L2924/0002
摘要： In a semi-conducting integrated circuit, there is made a light detection circuit, the output signal of which can be used to counter manipulations by dishonest persons who undertake a decapsulation or a removal from the card when the integrated circuit is inserted in a bank type card, or even a depassivation of the upper protective layer of this integrated circuit, in order to reveal the secret functioning of the circuit or to modify its characteristics. The detector comprises a current generator delivering a current of limited intensity which flows into a reversed biased electronic junction. When the junction is subjected to light, the reverse current that can be allowed into the junction increases. Since the current generator is not capable of putting through stronger current, the voltage at the terminals of the junction drops. This drop in voltage is used as information that reveals the illumination.
摘要翻译：在半导体集成电路中，形成光检测电路，其输出信号可用于对集成电路插入银行类型中进行解封装或从卡中取出的不诚实的人进行操纵卡，甚至是该集成电路的上保护层的去激活，以揭示电路的秘密功能或修改其特性。该检测器包括传递有限强度的电流的电流发生器，其流入反向偏置的电子结。当结点经受光时，可以允许进入结的反向电流增加。由于电流发生器不能施加更强的电流，所以结点的电压下降。这种电压下降被用作显示照明的信息。

7. 发明申请

US20070175994A1 METHOD AND APPARATUS FOR A USB AND CONTACTLESS SMART CARD DEVICE 有权
标题翻译： USB和无连接智能卡设备的方法和装置
公开(公告)号：US20070175994A1
公开(公告)日：2007-08-02
申请号：US11733528
申请日：2007-04-10
申请人： Serge Fruhauf
发明人： Serge Fruhauf
IPC分类号： G06K7/00 , G06K7/08
CPC分类号： G06K19/07739 , G06K19/077 , G06K19/07733 , G06K19/07769
摘要： An apparatus for a Universal Serial Bus (USB) and wireless smart card is provided. The apparatus includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. Furthermore, an apparatus for a triple-mode smart card is also provided herein. The apparatus for the triple mode smart card includes a mode detection circuit, a switching block, a controller, an antenna, and a wired interface. The apparatus for the triple mode smart card operates in one of a wireless mode, a USB mode and an International Standards Organization 7816 mode or other wired mode. Furthermore, the apparatus for any of these smart cards could operate in both the wireless and wired mode(s) without conflict, and without switching power off and on to change configuration.
摘要翻译：提供了一种用于通用串行总线（USB）和无线智能卡的装置。该装置包括模式检测电路，切换块，控制器，天线和有线接口。此外，本文还提供了一种用于三模式智能卡的装置。用于三重模式智能卡的装置包括模式检测电路，切换块，控制器，天线和有线接口。用于三模式智能卡的装置以无线模式，USB模式和国际标准组织7816模式或其他有线模式中的一种操作。此外，用于任何这些智能卡的装置可以在无冲突的情况下以无线和有线模式工作，并且不断开和断电以改变配置。

8. 发明授权

US5144515A Detector of fast variation in the supply of integrated circuits 失效
标题翻译：集成电路供应中快速变化的检测器
公开(公告)号：US5144515A
公开(公告)日：1992-09-01
申请号：US624336
申请日：1990-12-07
申请人： Serge Fruhauf , Freeric Breugnot
发明人： Serge Fruhauf , Freeric Breugnot
IPC分类号： G01R19/12 , G06F11/00 , G06K19/073 , G11C5/14
CPC分类号： G06K19/0701 , G01R19/12 , G06F11/00 , G06K19/073 , G11C5/143
摘要： Some integrated circuits need to be protected against malfunctioning due to the variations in the supply voltage Vcc. A detector of fast variations of the supply voltage is placed in the integrated circuit to interrupt or modify all or a part of the working of the general integrated circuit in the event of the occurrence of fast variation in Vcc. The detector includes a capacitor, a current limiter, a charging circuit, and a detection transistor. The current limiter is a transistor mounted as a diode. The charging circuit uses the supply voltage to charge the capacitor through the current limiter. The relatively stable voltage of the capacitor is applied to the gate of the detection transistor, which has a threshold voltage Vtp. The source of the detection transistor is connected to the voltage supply Vcc. If Vcc varies suddenly, the detector is made conductive. The assembly uses the difference between the threshold voltage Vtn of the current limiter and the threshold voltage Vtp of the detection transistor.
摘要翻译：由于电源电压Vcc的变化，需要保护某些集成电路免受故障的影响。在Vcc发生快速变化的情况下，电源电压快速变化的检测器被放置在集成电路中以中断或修改通用集成电路的全部或一部分工作。检测器包括电容器，限流器，充电电路和检测晶体管。电流限制器是作为二极管安装的晶体管。充电电路使用电源电压通过限流器对电容器充电。电容器的相对稳定的电压被施加到具有阈值电压Vtp的检测晶体管的栅极。检测晶体管的源极连接到电压源Vcc。如果Vcc突然变化，则检测器导通。组件使用限流器的阈值电压Vtn与检测晶体管的阈值电压Vtp之间的差。

9. 发明授权

US4860258A Electrically programmable non-volatile memory having sequentially deactivated write circuits 失效
标题翻译：电可编程的非易失性存储器具有顺序取消写入电路
公开(公告)号：US4860258A
公开(公告)日：1989-08-22
申请号：US110274
申请日：1987-10-20
申请人： Serge Fruhauf , Alexis Marquot
发明人： Serge Fruhauf , Alexis Marquot
IPC分类号： G11C17/00 , G11C16/10 , G11C16/26
CPC分类号： G11C16/10 , G11C16/26
摘要： An electrically programmable non-volatile memory includes a matrix of memory cells accessible by rows and columns, write and read circuits which apply potentials, representing the programmed datum or representing the read command, to the rows and columns. The memory also includes a device which controls the interconnection of the write and read circuits with the memory cells, wherein N memory cells are programmed simultaneously, N being greater than 1, each memory cell setting up a current surge when it is programmed at "1". The memory also includes a device for deactivating, one by one, the write circuits corresponding to the N memory cells where there is a change-over from a programming mode to a read mode, and a structure to short-circuit the deactivation device at the change-over to the programming mode.
摘要翻译：电可编程非易失性存储器包括可由行和列访问的存储器单元的矩阵，写入和读取电路，其将表示编程的数据或表示读取命令的电位施加到行和列。存储器还包括控制写入和读取电路与存储器单元的互连的装置，其中N个存储器单元被同时编程，N大于1，每个存储器单元在编程为“1”时设置电流浪涌 “。存储器还包括用于逐个去激活对应于从编程模式到读取模式的转换的N个存储器单元的写入电路的装置，以及用于将停用装置短路的结构切换到编程模式。

10. 发明授权

US4835423A MOS technology voltage switch-over circuit 失效
标题翻译： MOS技术电压切换电路
公开(公告)号：US4835423A
公开(公告)日：1989-05-30
申请号：US122445
申请日：1987-11-19
申请人： Gerard S. de Ferron , Serge Fruhauf
发明人： Gerard S. de Ferron , Serge Fruhauf
IPC分类号： G06F3/02 , H03K17/10 , H03K17/693
CPC分类号： H03K17/102 , H03K17/693
摘要： A voltage switch-over circuit, depending on a switch-over signal, delivers either a first voltage Vpp or a second voltage Vcc at its output, the voltage Vpp being greater than the voltage Vcc. The said circuit consists of a first MOS transistor with one of its electrodes connected to the voltage Vcc and a set of two series-connected MOS transistors with one of their electrodes connected to the voltage Vpp and with their two gates connected together so as to create a floating node at the common point between the two MOS transistors, the other electrode of the first MOS transistor and the other electrode of the set of two MOS transistors being connected together, and the gates of the first MOS transistor and those of the set of two MOS transistors respectively receiving the switch-over signal and the reverse switch-over signal.
摘要翻译：根据切换信号的电压切换电路在其输出处提供第一电压Vpp或第二电压Vcc，电压Vpp大于电压Vcc。所述电路包括一个第一MOS晶体管，其一个电极连接到电压Vcc，一组两个串联连接的MOS晶体管，其一个电极连接到电压Vpp，其两个栅极连接在一起，以产生在两个MOS晶体管之间的公共点处的浮动节点，第一MOS晶体管的另一个电极和两个MOS晶体管的另一个电极连接在一起，并且第一MOS晶体管的栅极和分别接收切换信号和反向切换信号的两个MOS晶体管。

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