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1. 发明授权

US06734815B1 Geometric D/A converter for a delay-locked loop 失效
标题翻译：用于延迟锁定环路的几何D / A转换器
公开(公告)号：US06734815B1
公开(公告)日：2004-05-11
申请号：US10396884
申请日：2003-03-25
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： H03M166
CPC分类号： H03M1/68 , H03M1/745
摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.
摘要翻译：几何DAC架构包括一系列基本相同的子DAC，每个子DAC具有n个抽头。子DAC从具有m =（所需抽头总数）/ n抽头的偏置DAC馈送。每个m个抽头的输出以k 的速率几何地增加。对于更简单的更传统的方法，几何DAC架构控制线期望仅需要（m + n）个抽头与（m×n）抽头相比较。此外，几何DAC架构比简单的更传统的方法需要更少的空间，由于它是模块化而容易扩展，并且产生总是单调的输出电流，而不管晶体管尺寸和PVT变化中的错误。通过在子DAC之间交替地反转n个控制线输入来编码n个抽头控制线，使得与几何DAC相关联的任何状态转换在每个控制线中仅发生一个位改变。

2. 发明授权

US06975260B1 Geometric D/A converter for a delay-locked loop 失效
标题翻译：用于延迟锁定环路的几何D / A转换器
公开(公告)号：US06975260B1
公开(公告)日：2005-12-13
申请号：US10986707
申请日：2004-11-12
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： H03M1/68 , H03M1/745
摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.
摘要翻译：几何DAC架构包括一系列基本相同的子DAC，每个子DAC具有n个抽头。子DAC从具有m =（所需抽头总数）/ n抽头的偏置DAC馈送。 m个抽头中的每一个的输出以几何的方式以k 的速率增加。对于更简单的更传统的方法，几何DAC架构控制线期望仅需要（m + n）个抽头与（m×n）抽头相比较。此外，几何DAC架构比简单的更传统的方法需要更少的空间，由于它是模块化而容易扩展，并且产生总是单调的输出电流，而不管晶体管尺寸和PVT变化中的错误。通过在子DAC之间交替地反转n个控制线输入来编码n个抽头控制线，使得与几何DAC相关联的任何状态转换在每个控制线中仅发生一个位改变。

3. 发明申请

US20120286856A1 PROGRAMMABLE NOISE FILTERING FOR BIAS KICKBACK DISTURBANCES 失效
标题翻译：可编程噪声滤波用于偏置KICKBACK干扰
公开(公告)号：US20120286856A1
公开(公告)日：2012-11-15
申请号：US13104899
申请日：2011-05-10
申请人： Hakan Dogan , Shahram Abdollahi-Alibeik
发明人： Hakan Dogan , Shahram Abdollahi-Alibeik
IPC分类号： H04B15/02
CPC分类号： H03H7/0153 , H03K5/24
摘要： A system and method are disclosed for reducing the kickback disturbance in an electronic circuit. The system is based on the coupling of a programmable noise filter between bias blocks. In one embodiment the programmable noise filter includes capacitors, resisters and switches and forms a C-R-C circuit structure. By selecting the resistance and capacitance values and the status of the switches, the performance of the programmable noise filter is determined. Also disclosed is a system and method to reduce kickback disturbances comprising N+1 bias blocks, N programmable noise filters, and a bias reference generator, wherein N is equal to or greater than one.
摘要翻译：公开了一种用于减小电子电路中的反冲扰的系统和方法。该系统基于偏置块之间的可编程噪声滤波器的耦合。在一个实施例中，可编程噪声滤波器包括电容器，电阻器和开关，并形成C-R-C电路结构。通过选择电阻和电容值以及开关的状态，确定可编程噪声滤波器的性能。还公开了一种减少包括N + 1个偏置块，N个可编程噪声滤波器和偏置参考发生器的反冲扰的系统和方法，其中N等于或大于1。

4. 发明申请

US20080181284A1 Hybrid Zero-IF Receiver 有权
标题翻译：混合零中频接收机
公开(公告)号：US20080181284A1
公开(公告)日：2008-07-31
申请号：US12016955
申请日：2008-01-18
申请人： Paul J. Husted , Shahram Abdollahi-Alibeik , David J. Weber , Soner Ozgur
发明人： Paul J. Husted , Shahram Abdollahi-Alibeik , David J. Weber , Soner Ozgur
IPC分类号： H04B1/69
CPC分类号： H04B1/30
摘要： An apparatus for processing a Bluetooth signal advantageously mixes down a received RF signal to an IF signal wherein one band-edge of the spectrum of the IF signal may be approximately 0 Hz. In one embodiment, the IF signal may be digitized, decimated and filtered before being processed into a baseband signal. The baseband signal may be processed by a cordic (COordinate Rotation DIgital Computer) processor to transform the baseband signal from rectangular to polar coordinates. A phase signal from the cordic processor may be used to determine transmitted Bluetooth data symbols. The apparatus may advantageously use less area than traditional Bluetooth receivers.
摘要翻译：用于处理蓝牙信号的装置有利地将所接收的RF信号与IF信号相混合，其中IF信号的频谱的一个带边可以为大约0Hz。在一个实施例中，IF信号可以在被处理成基带信号之前被数字化，抽取和滤波。基带信号可以由Cordic（Coordinate Rotation DIgital Computer）处理器处理，以将基带信号从矩形变换为极坐标。可以使用来自Cordic处理器的相位信号来确定所发送的蓝牙数据符号。该装置可以有利地使用比传统蓝牙接收机更少的面积。

5. 发明授权

US06947349B1 Apparatus and method for producing an output clock pulse and output clock generator using same 失效
标题翻译：用于产生输出时钟脉冲和使用其的输出时钟发生器的装置和方法
公开(公告)号：US06947349B1
公开(公告)日：2005-09-20
申请号：US10654258
申请日：2003-09-03
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： G11C8/00 , G11C11/419 , G11C29/02
CPC分类号： G11C29/12015 , G11C11/41 , G11C11/419 , G11C29/02 , G11C29/028 , G11C29/1201 , G11C29/50012
摘要： A method and apparatus generates output clock pulses, having leading and trailing edges that are adjusted in a pulse forming processor, according to the relative phase of an output clock and output data. Dynamic adjustment of the leading and trailing edges of output clock pulses improves the performance of high-speed devices significantly.
摘要翻译：一种方法和装置根据输出时钟和输出数据的相对相位产生具有在脉冲形成处理器中调整的前沿和后沿的输出时钟脉冲。输出时钟脉冲的前沿和后沿的动态调整显着提高了高速器件的性能。

6. 发明授权

US08547169B2 Programmable noise filtering for bias kickback disturbances 失效
标题翻译：用于偏置反冲扰动的可编程噪声滤波
公开(公告)号：US08547169B2
公开(公告)日：2013-10-01
申请号：US13104899
申请日：2011-05-10
申请人： Hakan Dogan , Shahram Abdollahi-Alibeik
发明人： Hakan Dogan , Shahram Abdollahi-Alibeik
IPC分类号： H03K5/00
CPC分类号： H03H7/0153 , H03K5/24
摘要： A system and method are disclosed for reducing the kickback disturbance in an electronic circuit. The system is based on the coupling of a programmable noise filter between bias blocks. In one embodiment the programmable noise filter includes capacitors, resisters and switches and forms a C-R-C circuit structure. By selecting the resistance and capacitance values and the status of the switches, the performance of the programmable noise filter is determined. Also disclosed is a system and method to reduce kickback disturbances comprising N+1 bias blocks, N programmable noise filters, and a bias reference generator, wherein N is equal to or greater than one.
摘要翻译：公开了一种用于减小电子电路中的反冲扰的系统和方法。该系统基于偏置块之间的可编程噪声滤波器的耦合。在一个实施例中，可编程噪声滤波器包括电容器，电阻器和开关，并形成C-R-C电路结构。通过选择电阻和电容值以及开关的状态，确定可编程噪声滤波器的性能。还公开了一种减少包括N + 1个偏置块，N个可编程噪声滤波器和偏置参考发生器的反冲扰的系统和方法，其中N等于或大于1。

7. 发明授权

US08295845B1 Transceiver I/Q mismatch calibration 有权
标题翻译：收发器I / Q不匹配校准
公开(公告)号：US08295845B1
公开(公告)日：2012-10-23
申请号：US12328128
申请日：2008-12-04
申请人： Shahram Abdollahi-Alibeik , Bemini Hennadige Janath Peiris
发明人： Shahram Abdollahi-Alibeik , Bemini Hennadige Janath Peiris
IPC分类号： H04W40/10
CPC分类号： H04B17/14 , H04B17/11
摘要： A calibration mechanism is disclosed for performing I/Q mismatch calibration operations in a wireless communication device comprising a receiver unit and a transmitter unit. During an I/Q mismatch calibration mode, a first signal and a second signal are provided from the transmitter unit to the receiver unit via a loopback path coupled between the transmitter and receiver units. A phase shift is added to the second signal that is provided to the receiver unit. A first set of I/Q measurements is determined from the first signal and a second set of I/Q measurements is determined from the second signal with the added phase shift. Transmitter and receiver I/Q mismatch parameters are calculated based on the first and second sets of I/Q measurements. The receiver and transceiver I/Q mismatch parameters are used to compensate for I/Q mismatch at the receiver and transmitter units, respectively.
摘要翻译：公开了一种用于在包括接收器单元和发射器单元的无线通信设备中执行I / Q失配校准操作的校准机构。在I / Q不匹配校准模式期间，经由耦合在发射机和接收机单元之间的环回路径，从发射机单元向接收机单元提供第一信号和第二信号。将相移添加到提供给接收器单元的第二信号。从第一信号确定第一组I / Q测量，并且从具有相加相移的第二信号确定第二组I / Q测量。基于I / Q测量的第一组和第二组来计算发射机和接收机I / Q失配参数。接收机和收发器I / Q失配参数分别用于补偿接收机和发射机单元的I / Q失配。

8. 发明授权

US06941417B1 High-speed low-power CAM-based search engine 失效
标题翻译：高速低功耗基于CAM的搜索引擎
公开(公告)号：US06941417B1
公开(公告)日：2005-09-06
申请号：US10017676
申请日：2001-12-14
申请人： Shahram Abdollahi-Alibeik , Mayur Vinod Joshi
发明人： Shahram Abdollahi-Alibeik , Mayur Vinod Joshi
IPC分类号： G06F12/00 , G11C15/00
CPC分类号： G11C15/00
摘要： The disclosed invention presents a method and apparatus to a one dimensional prefix search problem. The problem consists looking up the best match to a word out of a table of one-dimensional prefixes. The invention addresses the problems with prior art of high power consumption, large silicon chip area for implementation and slow search speed. The prefix entries are divided in several subgroups. A function is described that can be efficiently implemented to determine which of these subgroups the presented word will find a best match in. Thus, it is necessary to search only this small subgroup of prefixes. This saves on power consumption as well as area. An efficient hardware embodiment of this idea which can search at a very high speed is also presented. The applications for this invention could include internet routing, telephone call routing and string matching.
摘要翻译：所公开的发明提供了一维前缀搜索问题的方法和装置。这个问题包括从一维前缀的表中查找一个单词的最佳匹配。本发明解决了高功耗现有技术的问题，实现的大芯片面积和搜索速度慢。前缀条目分为几个子组。描述了可以有效地实现的功能，以确定所呈现的单词中哪个子组将找到最佳匹配。因此，仅需要搜索该小子组的前缀。这节省了功耗以及面积。还提出了可以以非常高的速度搜索的这种想法的高效硬件实施例。本发明的应用可以包括互联网路由，电话呼叫路由和字符串匹配。

9. 发明授权

US08144811B2 Hybrid zero-IF receiver 有权
标题翻译：混合零中频接收机
公开(公告)号：US08144811B2
公开(公告)日：2012-03-27
申请号：US12016955
申请日：2008-01-18
申请人： Paul J. Husted , Shahram Abdollahi-Alibeik , David J. Weber , Soner Ozgur
发明人： Paul J. Husted , Shahram Abdollahi-Alibeik , David J. Weber , Soner Ozgur
IPC分类号： H03K9/00
CPC分类号： H04B1/30
摘要： An apparatus for processing a Bluetooth signal advantageously mixes down a received RF signal to an IF signal wherein one band-edge of the spectrum of the IF signal may be approximately 0 Hz. In one embodiment, the IF signal may be digitized, decimated and filtered before being processed into a baseband signal. The baseband signal may be processed by a cordic (COordinate Rotation DIgital Computer) processor to transform the baseband signal from rectangular to polar coordinates. A phase signal from the cordic processor may be used to determine transmitted Bluetooth data symbols. The apparatus may advantageously use less area than traditional Bluetooth receivers.
摘要翻译：用于处理蓝牙信号的装置有利地将所接收的RF信号与IF信号相混合，其中IF信号的频谱的一个带边可以为大约0Hz。在一个实施例中，IF信号可以在被处理成基带信号之前被数字化，抽取和滤波。基带信号可以由Cordic（Coordinate Rotation DIgital Computer）处理器处理，以将基带信号从矩形变换为极坐标。可以使用来自Cordic处理器的相位信号来确定所发送的蓝牙数据符号。该装置可以有利地使用比传统蓝牙接收机更少的面积。

10. 发明授权

US07526603B1 High-speed low-power CAM-based search engine 失效
标题翻译：高速低功耗基于CAM的搜索引擎
公开(公告)号：US07526603B1
公开(公告)日：2009-04-28
申请号：US11116756
申请日：2005-04-28
申请人： Shahram Abdollahi-Alibeik , Mayur Vinod Joshi
发明人： Shahram Abdollahi-Alibeik , Mayur Vinod Joshi
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： The disclosed invention presents a method and apparatus to a one dimensional prefix search problem. The problem consists looking up the best match to a word out of a table of one-dimensional prefixes. The invention addresses the problems with prior art of high power consumption, large silicon chip area for implementation and slow search speed. The prefix entries are divided in several subgroups. A function is described that can be efficiently implemented to determine which of these subgroups the presented word will find a best match in. Thus, it is necessary to search only this small subgroup of prefixes. This saves on power consumption as well as area. An efficient hardware embodiment of this idea which can search at a very high speed is also presented. The applications for this invention could include internet routing, telephone call routing and string matching.
摘要翻译：所公开的发明提供了一维前缀搜索问题的方法和装置。这个问题包括从一维前缀的表中查找一个单词的最佳匹配。本发明解决了高功耗现有技术的问题，实现的大芯片面积和搜索速度慢。前缀条目分为几个子组。描述了可以有效地实现的功能，以确定所呈现的单词中哪个子组将找到最佳匹配。因此，仅需要搜索该小子组的前缀。这节省了功耗以及面积。还提出了可以以非常高的速度搜索的这种想法的高效硬件实施例。本发明的应用可以包括互联网路由，电话呼叫路由和字符串匹配。

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