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1. 发明申请

US20050147100A1 Dynamic management of TCP reassembly buffers 失效
标题翻译： TCP重组缓冲区的动态管理
公开(公告)号：US20050147100A1
公开(公告)日：2005-07-07
申请号：US10752921
申请日：2004-01-07
申请人： Giora Biran , Mark Epshtein , Vadim Makhervaks , Alexander Mesh , Tal Sostheim , Shaul Yifrach
发明人： Giora Biran , Mark Epshtein , Vadim Makhervaks , Alexander Mesh , Tal Sostheim , Shaul Yifrach
IPC分类号： G06F12/02 , H04L12/56 , H04L29/06 , H04L12/28
CPC分类号： H04L69/16 , G06F12/023 , H04L47/10 , H04L47/193 , H04L47/34 , H04L49/90 , H04L49/901 , H04L49/9084 , H04L49/9094 , H04L69/161 , H04L69/163
摘要： A method and system for dynamic management of Transmission Control Protocol (TCP) reassembly buffers in hardware (e.g., in a TCP/IP offload engine (TOE)). The method comprises: providing a plurality of data blocks and an indirect list; pointing, via entries in the indirect list, to allocated data blocks in the plurality of data blocks that currently store incoming data; if a free data block in the plurality of data blocks is required for the storage of incoming data, allocating the free data block for storing incoming data; and, if an allocated data block in the plurality of data blocks is no longer needed for storing incoming data, deallocating the allocated data block such that the deallocated data block becomes a free data block.
摘要翻译：用于在硬件中（例如，在TCP / IP卸载引擎（TOE））中的传输控制协议（TCP）重组缓冲器的动态管理的方法和系统。该方法包括：提供多个数据块和间接列表; 通过间接列表中的条目指向当前存储输入数据的多个数据块中的分配数据块; 如果需要多个数据块中的空闲数据块来存储输入数据，则分配用于存储输入数据的空闲数据块; 并且如果不再需要多个数据块中的分配的数据块来存储输入数据，则将所分配的数据块解除分配，使得解除分配的数据块变为空闲数据块。

2. 发明申请

US20130036271A1 DYNAMIC INDEX SELECTION IN A HARDWARE CACHE 有权
标题翻译：硬件缓存中的动态索引选择
公开(公告)号：US20130036271A1
公开(公告)日：2013-02-07
申请号：US13196071
申请日：2011-08-02
申请人： MVV A. Krishna , Shaul Yifrach
发明人： MVV A. Krishna , Shaul Yifrach
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0864 , G06F12/0895 , G06F2212/601
摘要： Systems and methods are disclosed for improving the performance of cache memory in a computer system by dynamically selecting an index for caching main memory while an application is running. A disclosed example of a memory system includes a cache including a data array, a primary tag array, and at least one secondary tag array. A currently selected index is used to index data bits to the data array and tag bits to the primary tag array. The performance of at least one candidate index is evaluated by indexing tag bits to the secondary tag array, without caching any data using the candidate index while the candidate index is under evaluation. If the candidate index has a better hit rate than the currently selected index, the memory system switches to using the candidate index to cache data.
摘要翻译：公开了用于通过在应用程序运行时动态选择缓存主存储器的索引来提高计算机系统中的高速缓冲存储器的性能的系统和方法。所公开的存储系统的示例包括包括数据阵列，主标签阵列和至少一个辅助标签阵列的高速缓存。当前选择的索引用于将数据位的数据位索引到主标记数组，并将标记位索引到主标记数组。通过将标签位索引到辅助标签数组来评估至少一个候选索引的性能，而候选索引正在评估中而不使用候选索引来缓存任何数据。如果候选索引具有比当前选择的索引更好的命中率，则存储器系统切换到使用候选索引来缓存数据。

3. 发明授权

US07734854B2 Device, system, and method of handling transactions 有权
标题翻译：设备，系统和处理事务的方法
公开(公告)号：US07734854B2
公开(公告)日：2010-06-08
申请号：US11969475
申请日：2008-01-04
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： G06F13/36
CPC分类号： G06F13/362
摘要： Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.
摘要翻译：一些实施例包括例如处理事务的设备，系统和方法。在一些说明性实施例中，处理计算系统中的事务的装置可以包括主单元，用于根据至少第一和第二仲裁方案通过请求总线发出读请求和写请求之间进行仲裁。由主单元根据第一仲裁方案发出的读和写请求之间的第一比率可以不同于主单元根据第二仲裁方案发出的读和写请求之间的第二比率。

4. 发明授权

US07496108B2 Method for dynamic management of TCP reassembly buffers 失效
标题翻译： TCP重组缓冲区的动态管理方法
公开(公告)号：US07496108B2
公开(公告)日：2009-02-24
申请号：US10752921
申请日：2004-01-07
申请人： Giora Biran , Mark Epshtein , Vadim Makhervaks , Alexander Mesh , Tal Sostheim , Shaul Yifrach
发明人： Giora Biran , Mark Epshtein , Vadim Makhervaks , Alexander Mesh , Tal Sostheim , Shaul Yifrach
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L69/16 , G06F12/023 , H04L47/10 , H04L47/193 , H04L47/34 , H04L49/90 , H04L49/901 , H04L49/9084 , H04L49/9094 , H04L69/161 , H04L69/163
摘要： A method for dynamic management of Transmission Control Protocol (TCP) reassembly buffers in hardware (e.g., in a TCP/IP offload engine (TOE)). The method comprises: providing a plurality of data blocks and an indirect list; pointing, via entries in the indirect list, to allocated data blocks in the plurality of data blocks that currently store incoming data; if a free data block in the plurality of data blocks is required for the storage of incoming data, allocating the free data block for storing incoming data; and, if an allocated data block in the plurality of data blocks is no longer needed for storing incoming data, deallocating the allocated data block such that the deallocated data block becomes a free data block.
摘要翻译：用于在硬件中（例如，在TCP / IP卸载引擎（TOE））中的传输控制协议（TCP）重组缓冲器的动态管理的方法。该方法包括：提供多个数据块和间接列表; 通过间接列表中的条目指向当前存储输入数据的多个数据块中的分配数据块; 如果需要多个数据块中的空闲数据块来存储输入数据，则分配用于存储输入数据的空闲数据块; 并且如果不再需要多个数据块中的分配的数据块来存储输入数据，则将所分配的数据块解除分配，使得解除分配的数据块变为空闲数据块。

5. 发明授权

US07747803B2 Device, system, and method of handling delayed transactions 有权
标题翻译：处理延迟交易的设备，系统和方法
公开(公告)号：US07747803B2
公开(公告)日：2010-06-29
申请号：US11946102
申请日：2007-11-28
申请人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
IPC分类号： G06F13/00 , G06F13/14 , G06F3/00
CPC分类号： G06F13/36
摘要： Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.
摘要翻译：处理延迟交易的设备，系统和方法。例如，在计算系统中处理延迟事务的装置包括：适于伪随机拒绝从主单元接收的请求的从单元。

6. 发明申请

US20090187870A1 PLACEMENT DRIVEN ROUTING 有权
标题翻译：放置驱动路由
公开(公告)号：US20090187870A1
公开(公告)日：2009-07-23
申请号：US12018422
申请日：2008-01-23
申请人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
发明人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items).
摘要翻译：一种根据集成电路规范布置布线的方法来创建集成电路设计。一旦初始放置的设计合法化，而不仅仅是启动布线路由，该方法可以识别集成电路设计中包含阻塞项目的书籍。该方法允许临时暂停路由进程，并将项目移动到一定程度。该移动过程被控制（根据相关书籍的信号功率输出而限制），使得集成电路设计的时序不受任何这种“中间路由”移动的影响。如果这些书没有任何封闭的物品，该过程将继续在物品和书籍之间布线。如果在电线路由之前或期间的任何一点，发现这些书籍确实有阻塞的项目，该过程将暂停线路的路由并执行任意数量的不同进程来解决阻塞的项目情况（解除阻塞的项目）。

7. 发明申请

US20090138641A1 Device, System, and Method of Handling Delayed Transactions 有权
标题翻译：设备，系统和处理延迟交易的方法
公开(公告)号：US20090138641A1
公开(公告)日：2009-05-28
申请号：US11946102
申请日：2007-11-28
申请人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
IPC分类号： G06F13/18
CPC分类号： G06F13/36
摘要： Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.
摘要翻译：处理延迟交易的设备，系统和方法。例如，在计算系统中处理延迟事务的装置包括：适于伪随机拒绝从主单元接收的请求的从单元。

8. 发明申请

US20200314011A1 FLEXIBLE SCHEME FOR ADDING RULES TO A NIC PIPELINE 审中-公开
公开(公告)号：US20200314011A1
公开(公告)日：2020-10-01
申请号：US16902371
申请日：2020-06-16
申请人： Manasi Deval , Elazar Cohen , Shaul Yifrach , Parthasarathy Sarangam
发明人： Manasi Deval , Elazar Cohen , Shaul Yifrach , Parthasarathy Sarangam
IPC分类号： H04L12/743 , H04L12/721 , H04L12/741 , H04L29/06
摘要： Flexible schemes for adding rules to a NIC pipeline and associated apparatus. Multiple match-action tables are implemented in host memory of a platform defining actions to be taken for matching packet flows. A packet processing pipeline and an exact match (EM) cache is implemented on a network interface, such as a NIC, installed in the platform. A portion of the match-action entries in the host memory match-action tables are cached in the EM cache. Received packets are processed to generate a key that is used as a lookup for the EM cache. If a match is found, the action is taken. For a miss, the key is forwarded to the host software and the match-action tables are searched. For a match, the action is taken, and the entry is added to the EM cache. If no match is found, a new match-action entry is added to a match-action table. Aging-out mechanisms are used for the match-action tables and the EM cache. A multi-hash scheme is used to that supports a very large number of match-action entries.

9. 发明申请

US20090185487A1 AUTOMATED ADVANCE LINK ACTIVATION 审中-公开
标题翻译：自动预警链接激活
公开(公告)号：US20090185487A1
公开(公告)日：2009-07-23
申请号：US12017432
申请日：2008-01-22
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： H04L1/00
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Embodiments herein provide a transaction level mechanism that ensures that the links are operational right in time for the data flow, so that the data flow will not be impacted by delays associated with link recovery into the operational state. The path has links that have the ability to be in an inactive mode or an active mode. The embodiments herein transmit an “activation transmission” over the path to turn on the links within the path, before sending a data transfer (comprising packetized data) to turn on (wake up) the inactive links within the path, so that the actual data transfer does not experience any such start-up or wake-up delays.
摘要翻译：这里的实施例提供了一种事务级别机制，其确保链路在时间上对于数据流动是正确的操作，使得数据流不会受到与链路恢复到操作状态相关联的延迟的影响。路径具有能够处于非活动模式或活动模式的链接。这里的实施例在发送数据传输（包括分组化数据）之前在路径内打开路径上的链路来传送“激活传输”，以打开（唤醒）路径内的非活动链路，使得实际数据转移不会发生任何此类启动或唤醒延迟。

10. 发明授权

US07562168B1 Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the same 失效
标题翻译：优化物理通信链路的虚拟通道的缓冲器使用的方法及其执行方法
公开(公告)号：US07562168B1
公开(公告)日：2009-07-14
申请号：US12128872
申请日：2008-05-29
申请人： Shaul Yifrach , Ilya Gransovky , Etai Adar , Giora Biran
发明人： Shaul Yifrach , Ilya Gransovky , Etai Adar , Giora Biran
IPC分类号： G06F3/00 , H04J3/16
CPC分类号： H04L47/30 , H04L47/10 , H04L49/90
摘要： Optimization of a use of memory buffers of a device connected to a physical link including virtual channels (VCs) while sustaining bandwidth for communication between the device and another entity, by determining an initial allocation of memory buffers of each VC. Further, the optimization is accomplished by determining whether a next VC is active or inactive. If the VC is determined to be inactive, a number of memory buffers initially allocated to the inactive channel is determined, and the memory buffers are re-allocated between the active VCs.
摘要翻译：通过确定每个VC的存储器缓冲器的初始分配，优化使用连接到包括虚拟通道（VC）的物理链路的设备的存储器缓冲器，同时维持设备与另一个实体之间的通信的带宽。此外，通过确定下一个VC是活动还是非活动来实现优化。如果VC被确定为不活动，则确定最初分配给非活动通道的多个存储器缓冲器，并且在活动VC之间重新分配存储器缓冲器。

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