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1. 发明授权

US07734854B2 Device, system, and method of handling transactions 有权
标题翻译：设备，系统和处理事务的方法
公开(公告)号：US07734854B2
公开(公告)日：2010-06-08
申请号：US11969475
申请日：2008-01-04
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： G06F13/36
CPC分类号： G06F13/362
摘要： Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.
摘要翻译：一些实施例包括例如处理事务的设备，系统和方法。在一些说明性实施例中，处理计算系统中的事务的装置可以包括主单元，用于根据至少第一和第二仲裁方案通过请求总线发出读请求和写请求之间进行仲裁。由主单元根据第一仲裁方案发出的读和写请求之间的第一比率可以不同于主单元根据第二仲裁方案发出的读和写请求之间的第二比率。

2. 发明申请

US20090185487A1 AUTOMATED ADVANCE LINK ACTIVATION 审中-公开
标题翻译：自动预警链接激活
公开(公告)号：US20090185487A1
公开(公告)日：2009-07-23
申请号：US12017432
申请日：2008-01-22
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： H04L1/00
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Embodiments herein provide a transaction level mechanism that ensures that the links are operational right in time for the data flow, so that the data flow will not be impacted by delays associated with link recovery into the operational state. The path has links that have the ability to be in an inactive mode or an active mode. The embodiments herein transmit an “activation transmission” over the path to turn on the links within the path, before sending a data transfer (comprising packetized data) to turn on (wake up) the inactive links within the path, so that the actual data transfer does not experience any such start-up or wake-up delays.
摘要翻译：这里的实施例提供了一种事务级别机制，其确保链路在时间上对于数据流动是正确的操作，使得数据流不会受到与链路恢复到操作状态相关联的延迟的影响。路径具有能够处于非活动模式或活动模式的链接。这里的实施例在发送数据传输（包括分组化数据）之前在路径内打开路径上的链路来传送“激活传输”，以打开（唤醒）路径内的非活动链路，使得实际数据转移不会发生任何此类启动或唤醒延迟。

3. 发明申请

US20090187683A1 ADAPTIVE LINK WIDTH CONTROL 审中-公开
标题翻译：自适应链路宽度控制
公开(公告)号：US20090187683A1
公开(公告)日：2009-07-23
申请号：US12017735
申请日：2008-01-22
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： G06F3/00
CPC分类号： H04L47/10 , H04L47/2416
摘要： A communications apparatus uses at least one logical communications link that comprises a plurality of lanes within a computerized hardware device. A data transfer monitor is connected to the logical communications link and measures the real-time data transfer bandwidth of the logical communications link. In addition, a link management unit or link width control unit (comparator) is connected to the lanes and to the data transfer monitor and continually compares the real-time data transfer bandwidth to a predetermined data transfer bandwidth standard. If the real-time data transfer bandwidth is below the predetermined data transfer bandwidth standard, the link management unit is adapted to perform up-configuring of the logical communications link by activating additional lanes up to a maximum number of lanes making up the logical communications link. Conversely, if the real-time data transfer bandwidth is above the predetermined data transfer bandwidth standard, the link management unit is adapted to perform down-configuring the logical communications link by deactivating lanes within the logical communications link. The lanes consume less power when the lanes are deactivated relative to when the lanes are activated, thus the down-configuring reduces power consumption.
摘要翻译：通信装置使用至少一个逻辑通信链路，其包括计算机化的硬件设备内的多条通道。数据传输监视器连接到逻辑通信链路，并测量逻辑通信链路的实时数据传输带宽。此外，链路管理单元或链路宽度控制单元（比较器）连接到通道和数据传输监视器，并将实时数据传输带宽连续地与预定的数据传输带宽标准进行比较。如果实时数据传输带宽低于预定的数据传输带宽标准，则链路管理单元适于通过激活附加通道来执行逻辑通信链路的上配置，最多数目的通道组成逻辑通信链路。相反，如果实时数据传输带宽高于预定的数据传输带宽标准，则链路管理单元适于通过停用逻辑通信链路内的通道来执行逻辑通信链路的下配置。当通道相对于通道被激活时，通道消耗较少的功率，因此下配置降低功耗。

4. 发明申请

US20090177822A1 Device, System, and Method of Handling Transactions 有权
标题翻译：设备，系统和处理交易的方法
公开(公告)号：US20090177822A1
公开(公告)日：2009-07-09
申请号：US11969475
申请日：2008-01-04
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： G06F13/18
CPC分类号： G06F13/362
摘要： Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.
摘要翻译：一些实施例包括例如处理事务的设备，系统和方法。在一些说明性实施例中，处理计算系统中的事务的装置可以包括主单元，用于根据至少第一和第二仲裁方案通过请求总线发出读请求和写请求之间进行仲裁。由主单元根据第一仲裁方案发出的读和写请求之间的第一比率可以不同于主单元根据第二仲裁方案发出的读和写请求之间的第二比率。

5. 发明授权

US07747803B2 Device, system, and method of handling delayed transactions 有权
标题翻译：处理延迟交易的设备，系统和方法
公开(公告)号：US07747803B2
公开(公告)日：2010-06-29
申请号：US11946102
申请日：2007-11-28
申请人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
IPC分类号： G06F13/00 , G06F13/14 , G06F3/00
CPC分类号： G06F13/36
摘要： Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.
摘要翻译：处理延迟交易的设备，系统和方法。例如，在计算系统中处理延迟事务的装置包括：适于伪随机拒绝从主单元接收的请求的从单元。

6. 发明申请

US20090138641A1 Device, System, and Method of Handling Delayed Transactions 有权
标题翻译：设备，系统和处理延迟交易的方法
公开(公告)号：US20090138641A1
公开(公告)日：2009-05-28
申请号：US11946102
申请日：2007-11-28
申请人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
IPC分类号： G06F13/18
CPC分类号： G06F13/36
摘要： Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.
摘要翻译：处理延迟交易的设备，系统和方法。例如，在计算系统中处理延迟事务的装置包括：适于伪随机拒绝从主单元接收的请求的从单元。

7. 发明授权

US07562168B1 Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the same 失效
标题翻译：优化物理通信链路的虚拟通道的缓冲器使用的方法及其执行方法
公开(公告)号：US07562168B1
公开(公告)日：2009-07-14
申请号：US12128872
申请日：2008-05-29
申请人： Shaul Yifrach , Ilya Gransovky , Etai Adar , Giora Biran
发明人： Shaul Yifrach , Ilya Gransovky , Etai Adar , Giora Biran
IPC分类号： G06F3/00 , H04J3/16
CPC分类号： H04L47/30 , H04L47/10 , H04L49/90
摘要： Optimization of a use of memory buffers of a device connected to a physical link including virtual channels (VCs) while sustaining bandwidth for communication between the device and another entity, by determining an initial allocation of memory buffers of each VC. Further, the optimization is accomplished by determining whether a next VC is active or inactive. If the VC is determined to be inactive, a number of memory buffers initially allocated to the inactive channel is determined, and the memory buffers are re-allocated between the active VCs.
摘要翻译：通过确定每个VC的存储器缓冲器的初始分配，优化使用连接到包括虚拟通道（VC）的物理链路的设备的存储器缓冲器，同时维持设备与另一个实体之间的通信的带宽。此外，通过确定下一个VC是活动还是非活动来实现优化。如果VC被确定为不活动，则确定最初分配给非活动通道的多个存储器缓冲器，并且在活动VC之间重新分配存储器缓冲器。

8. 发明授权

US07827325B2 Device, system, and method of speculative packet transmission 有权
标题翻译：设备，系统和推测分组传输的方法
公开(公告)号：US07827325B2
公开(公告)日：2010-11-02
申请号：US11931689
申请日：2007-10-31
申请人： Etai Adar , Ilya Granovsky , Zorik Machulsky , Paul J. Mattos
发明人： Etai Adar , Ilya Granovsky , Zorik Machulsky , Paul J. Mattos
IPC分类号： G06F13/38
CPC分类号： G06F13/387
摘要： A mechanism for speculative packet transmission including a credit-based flow control interconnect device to initiate speculative transmission of a Transaction Layer Packet if the number of available flow control (FC) credits is insufficient for completing the transmission. The sending device initiates a speculative transmission of packets to the receiving device even though the packet for transmission requires a number of FC credits greater than the available FC credits. If the additional FC credits required to complete the packet transmission become available to the sending device before the transmission is completed, the packets are then fully transmitted by the sending device. Otherwise, if the additional FC credits required do not become available prior to completion of the transmission, then the sending device aborts the transmission without utilization of the FC credits. The sending device may initiate speculative packet transmission only if a particular minimal amount of FC credits is available.
摘要翻译：一种用于推测分组传输的机制，包括基于信用的流控制互连设备，用于如果可用流控制（FC）信用的数量不足以完成传输，则启动事务层分组的推测传输。发送设备发起分组到接收设备的推测传输，即使用于传输的分组需要大于可用FC信用的多个FC信用。如果完成分组传输所需的附加FC信用在发送完成之前对发送设备可用，则发送设备将完全发送分组。否则，如果在完成传输之前所需的附加FC信用不可用，则发送设备在不使用FC信用的情况下中止传输。只有当特定的最小量的FC信用可用时，发送设备才能启动推测性分组传输。

9. 发明授权

US09032102B2 Decode data for fast PCI express multi-function device address decode 有权
标题翻译：解码数据，实现快速PCI Express多功能设备地址解码
公开(公告)号：US09032102B2
公开(公告)日：2015-05-12
申请号：US13411203
申请日：2012-03-02
申请人： Ilya Granovsky , Etai Adar
发明人： Ilya Granovsky , Etai Adar
IPC分类号： G06F13/36 , G06F9/30
CPC分类号： G06F9/30145 , G06F13/36 , G06F13/385
摘要： An apparatus and method of fast PCIe multi-function device address decode utilizing a target function data look up table. One or more decode directives (e.g., targeted functions) are provided within the PCIe request packet, thereby eliminating the need for target function search during the decode process in the endpoint device. This enables single-decoder single-step decode implementation in complex multi-function devices.
摘要翻译：一种使用目标功能数据查找表的快速PCIe多功能设备地址解码的设备和方法。在PCIe请求分组内提供一个或多个解码指令（例如，目标函数），从而消除在端点设备中的解码过程期间对目标函数搜索的需要。这使得复杂多功能设备中的单解码器单步解码实现成为可能。

10. 发明申请

US20130232279A1 Decode Data for Fast PCI Express Multi-Function Device Address Decode 有权
标题翻译：解码快速PCI Express多功能设备地址解码数据
公开(公告)号：US20130232279A1
公开(公告)日：2013-09-05
申请号：US13411203
申请日：2012-03-02
申请人： Etai Adar , Ilya Granovsky
发明人： Etai Adar , Ilya Granovsky
IPC分类号： G06F13/36 , G06F3/00
CPC分类号： G06F9/30145 , G06F13/36 , G06F13/385
摘要： An apparatus and method of fast PCIe multi-function device address decode utilizing a target function data look up table. One or more decode directives (e.g., targeted functions) are provided within the PCIe request packet, thereby eliminating the need for target function search during the decode process in the endpoint device. This enables single-decoder single-step decode implementation in complex multi-function devices.
摘要翻译：一种使用目标功能数据查找表的快速PCIe多功能设备地址解码的设备和方法。在PCIe请求分组内提供一个或多个解码指令（例如，目标函数），从而消除在端点设备中的解码过程期间对目标函数搜索的需要。这使得复杂多功能设备中的单解码器单步解码实现成为可能。

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