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1. 发明申请

US20090185487A1 AUTOMATED ADVANCE LINK ACTIVATION 审中-公开
标题翻译：自动预警链接激活
公开(公告)号：US20090185487A1
公开(公告)日：2009-07-23
申请号：US12017432
申请日：2008-01-22
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： H04L1/00
CPC分类号： G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Embodiments herein provide a transaction level mechanism that ensures that the links are operational right in time for the data flow, so that the data flow will not be impacted by delays associated with link recovery into the operational state. The path has links that have the ability to be in an inactive mode or an active mode. The embodiments herein transmit an “activation transmission” over the path to turn on the links within the path, before sending a data transfer (comprising packetized data) to turn on (wake up) the inactive links within the path, so that the actual data transfer does not experience any such start-up or wake-up delays.
摘要翻译：这里的实施例提供了一种事务级别机制，其确保链路在时间上对于数据流动是正确的操作，使得数据流不会受到与链路恢复到操作状态相关联的延迟的影响。路径具有能够处于非活动模式或活动模式的链接。这里的实施例在发送数据传输（包括分组化数据）之前在路径内打开路径上的链路来传送“激活传输”，以打开（唤醒）路径内的非活动链路，使得实际数据转移不会发生任何此类启动或唤醒延迟。

2. 发明授权

US07500062B2 Fast path memory read request processing in a multi-level memory architecture 有权
标题翻译：快速路径存储器在多级存储器架构中的读请求处理
公开(公告)号：US07500062B2
公开(公告)日：2009-03-03
申请号：US11282093
申请日：2005-11-17
申请人： Bruce Leroy Beukema , Michael Bar-Joshua , Alexander Mesh , Shaul Yifrach
发明人： Bruce Leroy Beukema , Michael Bar-Joshua , Alexander Mesh , Shaul Yifrach
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F9/3834 , G06F12/126
摘要： A circuit arrangement and method selectively reorder speculatively issued memory read requests being communicated to a lower memory level in a multi-level memory architecture. In particular, a memory read request that has been speculatively issued to a lower memory level prior to completion of a cache lookup operation initiated in a cache memory in a higher memory level may be reordered ahead of at least one previously received and pending request awaiting communication to the lower memory level. By doing so, the latency associated with the memory read request is reduced when the request results in a cache miss in the higher level memory, and as a result, system performance is improved.
摘要翻译：电路布置和方法选择性地重新排序在多级存储器体系结构中被推送的存储器读请求被传送到较低存储器级。特别地，在高级存储器级别的高速缓冲存储器中启动的高速缓存查找操作完成之前被推测地发布到较低存储器级别的存储器读取请求可以在至少一个先前接收到的等待通信的等待请求之前重新排序到较低的内存级别。通过这样做，当请求导致高级存储器中的高速缓存未命中时，与存储器读取请求相关联的延迟被减少，结果提高了系统性能。

3. 发明授权

US07747803B2 Device, system, and method of handling delayed transactions 有权
标题翻译：处理延迟交易的设备，系统和方法
公开(公告)号：US07747803B2
公开(公告)日：2010-06-29
申请号：US11946102
申请日：2007-11-28
申请人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
IPC分类号： G06F13/00 , G06F13/14 , G06F3/00
CPC分类号： G06F13/36
摘要： Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.
摘要翻译：处理延迟交易的设备，系统和方法。例如，在计算系统中处理延迟事务的装置包括：适于伪随机拒绝从主单元接收的请求的从单元。

4. 发明申请

US20090187870A1 PLACEMENT DRIVEN ROUTING 有权
标题翻译：放置驱动路由
公开(公告)号：US20090187870A1
公开(公告)日：2009-07-23
申请号：US12018422
申请日：2008-01-23
申请人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
发明人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items).
摘要翻译：一种根据集成电路规范布置布线的方法来创建集成电路设计。一旦初始放置的设计合法化，而不仅仅是启动布线路由，该方法可以识别集成电路设计中包含阻塞项目的书籍。该方法允许临时暂停路由进程，并将项目移动到一定程度。该移动过程被控制（根据相关书籍的信号功率输出而限制），使得集成电路设计的时序不受任何这种“中间路由”移动的影响。如果这些书没有任何封闭的物品，该过程将继续在物品和书籍之间布线。如果在电线路由之前或期间的任何一点，发现这些书籍确实有阻塞的项目，该过程将暂停线路的路由并执行任意数量的不同进程来解决阻塞的项目情况（解除阻塞的项目）。

5. 发明申请

US20090138641A1 Device, System, and Method of Handling Delayed Transactions 有权
标题翻译：设备，系统和处理延迟交易的方法
公开(公告)号：US20090138641A1
公开(公告)日：2009-05-28
申请号：US11946102
申请日：2007-11-28
申请人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Atar Peyser , Shaul Yifrach
IPC分类号： G06F13/18
CPC分类号： G06F13/36
摘要： Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.
摘要翻译：处理延迟交易的设备，系统和方法。例如，在计算系统中处理延迟事务的装置包括：适于伪随机拒绝从主单元接收的请求的从单元。

6. 发明授权

US08249177B2 Detection of frame marker quality 失效
标题翻译：检测帧标记质量
公开(公告)号：US08249177B2
公开(公告)日：2012-08-21
申请号：US12397790
申请日：2009-03-04
申请人： Etai Adar , Michael Bar-Joshua , David Stauffer
发明人： Etai Adar , Michael Bar-Joshua , David Stauffer
IPC分类号： H04L27/00
CPC分类号： H04L7/042 , H04L1/20 , H04L7/046
摘要： For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.
摘要翻译：例如，检测帧标记质量的方法包括：在从第一分量发送到公共硬件单元的第二分量的比特流中检测具有不同于由通信协议; 以及基于所述位模式和所述未损坏帧标记的位模式之间的差异，将质量水平指示符分配给帧标记。

7. 发明授权

US07904865B2 Placement driven routing 有权
标题翻译：放置驱动路由
公开(公告)号：US07904865B2
公开(公告)日：2011-03-08
申请号：US12018422
申请日：2008-01-23
申请人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
发明人： Shaul Yifrach , Michael Bar-Joshua , Itamar Tsachi , Boaz Yeger
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items).
摘要翻译：一种根据集成电路规范布置布线的方法来创建集成电路设计。一旦初始放置的设计合法化，而不仅仅是启动布线路由，该方法可以识别集成电路设计中包含阻塞项目的书籍。该方法允许临时暂停路由进程，并将项目移动到一定程度。该移动过程被控制（根据相关书籍的信号功率输出而限制），使得集成电路设计的时序不受任何这种“中间路由”移动的影响。如果这些书没有任何封闭的物品，该过程将继续在物品和书籍之间布线。如果在电线路由之前或期间的任何一点，发现这些书籍确实有阻塞的项目，该过程将暂停线路的路由并执行任意数量的不同进程来解决阻塞的项目情况（解除阻塞的项目）。

8. 发明申请

US20090187683A1 ADAPTIVE LINK WIDTH CONTROL 审中-公开
标题翻译：自适应链路宽度控制
公开(公告)号：US20090187683A1
公开(公告)日：2009-07-23
申请号：US12017735
申请日：2008-01-22
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： G06F3/00
CPC分类号： H04L47/10 , H04L47/2416
摘要： A communications apparatus uses at least one logical communications link that comprises a plurality of lanes within a computerized hardware device. A data transfer monitor is connected to the logical communications link and measures the real-time data transfer bandwidth of the logical communications link. In addition, a link management unit or link width control unit (comparator) is connected to the lanes and to the data transfer monitor and continually compares the real-time data transfer bandwidth to a predetermined data transfer bandwidth standard. If the real-time data transfer bandwidth is below the predetermined data transfer bandwidth standard, the link management unit is adapted to perform up-configuring of the logical communications link by activating additional lanes up to a maximum number of lanes making up the logical communications link. Conversely, if the real-time data transfer bandwidth is above the predetermined data transfer bandwidth standard, the link management unit is adapted to perform down-configuring the logical communications link by deactivating lanes within the logical communications link. The lanes consume less power when the lanes are deactivated relative to when the lanes are activated, thus the down-configuring reduces power consumption.
摘要翻译：通信装置使用至少一个逻辑通信链路，其包括计算机化的硬件设备内的多条通道。数据传输监视器连接到逻辑通信链路，并测量逻辑通信链路的实时数据传输带宽。此外，链路管理单元或链路宽度控制单元（比较器）连接到通道和数据传输监视器，并将实时数据传输带宽连续地与预定的数据传输带宽标准进行比较。如果实时数据传输带宽低于预定的数据传输带宽标准，则链路管理单元适于通过激活附加通道来执行逻辑通信链路的上配置，最多数目的通道组成逻辑通信链路。相反，如果实时数据传输带宽高于预定的数据传输带宽标准，则链路管理单元适于通过停用逻辑通信链路内的通道来执行逻辑通信链路的下配置。当通道相对于通道被激活时，通道消耗较少的功率，因此下配置降低功耗。

9. 发明申请

US20090177822A1 Device, System, and Method of Handling Transactions 有权
标题翻译：设备，系统和处理交易的方法
公开(公告)号：US20090177822A1
公开(公告)日：2009-07-09
申请号：US11969475
申请日：2008-01-04
申请人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
发明人： Etai Adar , Michael Bar-Joshua , Ilya Granovsky , Shaul Yifrach
IPC分类号： G06F13/18
CPC分类号： G06F13/362
摘要： Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.
摘要翻译：一些实施例包括例如处理事务的设备，系统和方法。在一些说明性实施例中，处理计算系统中的事务的装置可以包括主单元，用于根据至少第一和第二仲裁方案通过请求总线发出读请求和写请求之间进行仲裁。由主单元根据第一仲裁方案发出的读和写请求之间的第一比率可以不同于主单元根据第二仲裁方案发出的读和写请求之间的第二比率。

10. 发明申请

US20080247316A1 Method Circuit and System for Data Flow Control 审中-公开
标题翻译：数据流控制方法电路与系统
公开(公告)号：US20080247316A1
公开(公告)日：2008-10-09
申请号：US11695681
申请日：2007-04-03
申请人： Michael Bar-Joshua , Bruce Leroy Beukema , Alexander Mesh , Shaul Yifrach
发明人： Michael Bar-Joshua , Bruce Leroy Beukema , Alexander Mesh , Shaul Yifrach
IPC分类号： H04N5/91
CPC分类号： H04N21/23406 , H04N7/17327 , H04N21/44004 , H04N21/6377 , H04N21/6583
摘要： Disclosed is a method and circuit for a receiver to receive data from an associated data transmitter. The receiver may include a signaling module adapted to transmit a Ready-To-Receive (“RTR”) signal to the associated transmitter when a number of vacant bits in a data buffer exceeds a delay associated value.
摘要翻译：公开了一种用于接收机从相关联的数据发射机接收数据的方法和电路。接收机可以包括适配成当数据缓冲器中的空闲位数超过延迟相关值时向相关联的发射机发送就绪接收（“RTR”）信号的信令模块。

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